Reconfigurable neuro-synaptic cores for spiking neural network

Patent metadata

Field	Value
Publication number	US-11195079-B2
Application number	US-201715821123-A
Country	US
Kind code	B2
Filing date	Nov 22, 2017
Priority date	Nov 22, 2017
Publication date	Dec 7, 2021
Grant date	Dec 7, 2021

Abstract

In one embodiment, a processor comprises a first neuro-synaptic core comprising first circuitry to configure the first neuro-synaptic core as a neuron core responsive to a first value specified by a configuration parameter; and configure the first neuro-synaptic core as a synapse core responsive to a second value specified by the configuration parameter.

First claim

What is claimed is:

1. A processor comprising:
a first neuro-synaptic core comprising circuitry to:
configure the first neuro-synaptic core as a neuron core responsive to a first value specified by a configuration parameter; and
configure the first neuro-synaptic core as a synapse core responsive to a second value specified by the configuration parameter, wherein configuring the first neuro-synaptic core as the neuron core comprises enabling neuron processing circuitry of the first neuro-synaptic core, the neuron processing circuitry to update neuron states, and wherein configuring the first neuro-synaptic core as the synapse core comprises disabling the neuron processing circuitry of the first neuro-synaptic core.

2. The processor of claim 1 , further comprising a second neuro-synaptic core comprising second circuitry to:
configure the second neuro-synaptic core as a neuron core responsive to the second value specified by the configuration parameter; and
configure the second neuro-synaptic core as a synapse core responsive to the first value specified by the configuration parameter.

3. The processor of claim 2 , wherein the first neuro-synaptic core comprises a first memory array and the second neuro-synaptic core comprises a second memory array, wherein the first memory array is larger than the second memory array.

4. The processor of claim 3 , wherein the first memory array is a static random access memory (SRAM) and the second memory array is a register file.

5. The processor of claim 3 , wherein the first memory array is a first portion of a shared memory and the second memory array is a second portion of the shared memory.

6. The processor of claim 1 , wherein the synapse core is to store synapse weights and the neuron core is to store neuron membrane potentials.

7. The processor of claim 1 , wherein the neuron core is to generate a neuron spike responsive to a neuron's membrane potential exceeding a threshold and send the neuron spike to a second neuro-synaptic core configured as a synapse core to access at least one synapse weight stored by the second neuro-synaptic core.

8. The processor of claim 1 , wherein the circuitry of the first neuro-synaptic core is to:
disable a second circuitry of the first neuro-synaptic core and enable a third circuitry of the first neuro-synaptic core responsive to the first value specified by the configuration parameter; and
disable the third circuitry and enable the second circuitry responsive to the second value specified by the configuration parameter.

9. The processor of claim 1 , wherein the configuration parameter is a global configuration parameter to specify whether a plurality of first neuro-synaptic cores of the processor are to be configured as neuron cores or synapse cores.

10. The processor of claim 1 , wherein the processor is to implement a feedforward neural network or a recurrent neural network during a period of time in which the configuration parameter specifies the second value.

11. The processor of claim 1 , wherein the processor is to implement a convolutional neural network during a period of time in which the configuration parameter specifies the first value.

12. The processor of claim 1 , wherein the first neuro-synaptic core is coupled to a plurality of neuro-synaptic cores of the processor via one or more routers of a network on chip.

13. A method comprising:
configuring, by circuitry, a first neuro-synaptic core as a neuron core responsive to a first value specified by a configuration parameter; and
configuring, by the circuitry, the first neuro-synaptic core as a synapse core responsive to a second value specified by the configuration parameter, wherein configuring the first neuro-synaptic core as the neuron core comprises enabling neuron processing circuitry of the first neuro-synaptic core, the neuron processing circuitry to update neuron states, and wherein configuring the first neuro-synaptic core as the synapse core comprises disabling the neuron processing circuitry of the first neuro-synaptic core.

14. The method of claim 13 , further comprising storing synapse weights by the synapse core and storing neuron membrane potentials by the neuron core.

15. The method of claim 13 , further comprising:
generating a neuron spike by the neuron core responsive to a neuron's membrane potential exceeding a threshold; and
sending the neuron spike to a second neuro-synaptic core configured as a synapse core to access at least one synapse weight stored by the second neuro-synaptic core.

16. The method of claim 13 , further comprising:
disabling a second circuitry of the first neuro-synaptic core and enabling a third circuitry of the first neuro-synaptic core responsive to the first value specified by the configuration parameter; and
disabling the third circuitry and enabling the second circuitry responsive to the second value specified by the configuration parameter.

17. A non-transitory machine readable storage medium having instructions stored thereon, the instructions when executed by a machine to cause the machine to:
access neural network parameters and configure a plurality of neuro-synaptic cores to implement a neural network specified by the neural network parameters; and
set, based on one or more of the neural network parameters, a configuration parameter to specify a first value or a second value, wherein circuitry of a first neuro-synaptic core of the plurality of neuro-synaptic cores is to:
configure the first neuro-synaptic core as a neuron core responsive to a first value specified by the configuration parameter; and
configure the first neuro-synaptic core as a synapse core responsive to a second value specified by the configuration parameter, wherein configuring the first neuro-synaptic core as the neuron core comprises enabling neuron processing circuitry of the first neuro-synaptic core, the neuron processing circuitry to update neuron states, and wherein configuring the first neuro-synaptic core as the synapse core comprises disabling the neuron processing circuitry of the first neuro-synaptic core.

18. The medium of claim 17 , wherein the synapse core is to store synapse weights and the neuron core is to store neuron membrane potentials.

19. The medium of claim 17 , wherein the neuron core is to generate a neuron spike responsive to a neuron's membrane potential exceeding a threshold and send the neuron spike to a second neuro-synaptic core configured as a synapse core to access at least one synapse weight stored by the second neuro-synaptic core.

20. The medium of claim 17 , wherein the circuitry of the first neuro-synaptic core is to:
disable a second circuitry of the first neuro-synaptic core and enable a third circuitry of the first neuro-synaptic core responsive to a first value specified by the configuration parameter; and
disable the third circuitry and enable the second circuitry responsive to a second value specified configuration parameter.

21. A system comprising:
a memory; and
a processor comprising a plurality of first neuro-synaptic cores;
wherein the processor is to:
set one or more configuration parameters, a configuration parameter to specify a first value or a second value;
cause the plurality of first neuro-synaptic cores to be configured as neuron cores responsive to the first value specified by the one or more configuration parameters; and
cause the plurality of first neuro-synaptic cores to be configured as synapse cores responsive to a second value specified by the one

Assignees

• Intel Corp

Inventors

• Sumbul Huseyin E
• Chen Gregory K
• Knag Phil
• Kumar Raghavan
• Krishnamurthy Ram K

Classifications

• G06N3/0464 Primary

  Convolutional networks [CNN, ConvNet] · CPC title

• G06N3/0495

  Quantised networks; Sparse networks; Compressed networks · CPC title

• G06N3/063

  using electronic means · CPC title

• G06N3/088

  Non-supervised learning, e.g. competitive learning · CPC title

• G06N3/049 Primary

  Temporal neural networks, e.g. delay elements, oscillating neurons or pulsed inputs · CPC title