Correlated double sampling analog-to-digital converter

Patent metadata

Field	Value
Publication number	US-11190197-B2
Application number	US-201916969829-A
Country	US
Kind code	B2
Filing date	Feb 19, 2019
Priority date	Feb 20, 2018
Publication date	Nov 30, 2021
Grant date	Nov 30, 2021

Abstract

Noise sources in a pipelined ADC circuit can include kT/C sampling noise from a capacitor DAC circuit and residue amplifier sampling noise. The kT/C sampling noise is inversely proportional to the size of the sampling capacitors; the larger sampling capacitors produce less noise. However, larger sampling capacitor can be difficult to drive and physically occupy significant die area. By using the described techniques, the inversely proportional relationship between the sampling noise and the size of the sampling capacitors is no longer true. The size of the sampling capacitors can be greats reduced, which can reduce the die area and reduce the power consumption of the ADC, and the kT/C sampling noise can be canceled using correlated double sampling (CDS) techniques.

First claim

The invention claimed is:

1. A method for performing analog-to-digital conversion, the method comprising:
coupling an analog input signal to a first ADC circuit of a first stage of a pipelined analog-to-digital (ADC) circuit and to a digital-to-analog converter (DAC) circuit of the first stage;
opening a switch to decouple the DAC circuit of the first stage from a bias voltage, the opening resulting in a noise charge onto the DAC: circuit of the first stage;
sampling a representation of the noise charge;
loading an output of the first ADC circuit of the first stage onto the DAC circuit of the first stage to generate a combination of a residue and the noise charge;
sampling a representation of the combination of the residue and the noise charge; and
determining a difference between the sampled representation of the noise charge and the sampled representation of the combination of the residue and the noise charge to cancel the noise charge.

2. The method of claim 1 , further comprising one or both of:
amplifying the noise charge prior to sampling the representation of the noise charge; and
amplifying the combination of the noise charge and the residue prior to sampling the representation of the combination of the residue and the noise charge.

3. The method of claim 1 , further comprising one or both of:
filtering the representation of the noise charge prior to sampling the representation of the noise charge; and
filtering the representation of the combination of the noise charge and the residue prior to sampling the representation of the combination of the residue and the noise charge.

4. The method of claim 3 , wherein filtering the representation of the noise charge and/or the representation of the combination of the residue and the noise charge includes:
settling a voltage; and
after settling, reducing a bandwidth to band limit the representation of the noise charge and/or the representation of the combination of the residue and the noise charge.

5. The method of claim 1 ,
wherein sampling the representation of the noise charge includes:
sampling the representation of the noise charge onto a second stage of the pipelined ADC circuit, and
wherein sampling the representation of the combination of the residue and the noise charge includes:
sampling the representation of combination of the noise charge and the residue onto the second stage.

6. The method of claim 1 , wherein the pipelined ADC circuit is a differential ADC circuit, and wherein coupling the analog input signal includes:
coupling a differential analog input signal.

7. A method for performing analog-to-digital conversion on an analog input signal, the method comprising:
coupling the analog input signal to an ADC circuit of a first stage of a pipelined analog-to-digital ADC circuit;
loading an output of the first ADC circuit of the first stage onto a DAC circuit of the first stage;
opening a switch to decouple the DAC circuit of the first stage from a bias voltage, the opening resulting in a noise charge onto the DAC circuit of the first stage;
sampling a representation of the noise charge;
coupling the analog input signal onto the DAC circuit of the first stage to generate a combination of a residue and the noise charge;
sampling a representation of the combination of the residue and the noise charge; and
determining a difference between the sampled representation of the noise charge and the sampled representation of the combination of the residue and the noise charge to cancel the noise charge.

8. The method of claim 7 , further comprising:
amplifying the noise charge prior to sampling the representation of the noise charge; and
amplifying the combination of the noise charge and the residue prior to sampling the representation of the combination of the residue and the noise charge.

9. The method of claim 7 , further comprising one or both of:
filtering the representation of the noise charge prior to sampling the representation of the noise charge; and
filtering the representation of the combination of the noise charge and the residue prior to sampling the representation of the combination of the residue and the noise charge.

10. The method of claim 9 , wherein filtering the representation of the noise charge and/or the representation of the combination of the residue and the noise charge includes:
settling a voltage; and

after settling, reducing a bandwidth to band limit, the representation of the noise charge and/or the representation of the combination of the residue and the noise charge.

11. The method of claim 7 , wherein sampling the representation of the noise charge includes:
sampling the noise charge onto a second stage of the pipelined ADC circuit, and
wherein sampling the representation of the combination of the residue and the noise charge includes:
sampling the representation of the combination of the noise charge and the residue onto the second stage.

12. The method of claim 7 , wherein the pipelined ADC circuit is a differential ADC circuit, and wherein coupling the analog input signal includes:
coupling a differential analog input signal.

13. A pipelined analog-to-digital converter (ADC) circuit comprising:
a first ADC circuit of a first stage of the pipelined ADC circuit;
a digital-to-analog converter (DAC) circuit coupled to an output of the first ADC; and
a control circuit configured to control operation of a plurality of switches to:
couple an analog input signal to the DAC circuit of the first stage and to the first ADC circuit of the first stage;
open a switch to decouple the DAC circuit of the first stage from a bias voltage, the opening resulting in a noise charge onto the DAC circuit of the first stage and a representation of the noise charge at the output of an amplifier circuit coupled to the DAC circuit;
sample the representation of the noise charge;
load an output of the first ADC circuit of the first stage onto the DAC circuit of the first stage to generate a representation of a combination of a residue and the noise charge at the output of the amplifier;
sample a representation of the combination of the residue and the noise charge; and
determine a difference between the sampled representation of the noise charge and the sampled representation of the combination of the residue and the noise charge to cancel the noise charge.

14. The pipelined ADC circuit of claim 13 , further comprising:
at least one impedance element coupled to the amplifier circuit in a negative feedback configuration.

15. The pipelined ADC of claim 14 , wherein the at least one impedance element includes a capacitor coupled between the output and the input of the amplifier to create a virtual ground at the input of the amplifier.

16. The pipelined ADC circuit of claim 13 , further comprising:
a dynamic filter, wherein the control circuit configured to control operation of the plurality of switches to sample the representation of the noise charge and to sample the representation of the combination of the residue and the noise charge is configured to control operation of the plurality of switches to:
filter the representation of the noise charge using the dynamic filter; and/or
filter the representation of the combination of the residue and the noise charge using the dynamic filter.

17. The pipelined ADC circuit of claim 13 , wherein the analog input signal is a differential analog input signal, and wherein the pipelined ADC circuit is arranged in a differential configuration.

18. A pipelined analog-to-digital conver

Assignees

• Analog Devices International Unlimited Co

Inventors

• Rajasekhar Sanjay
• Maurino Roberto Sergio Matteo

Classifications

• H03M1/0607 Primary

  Offset or drift compensation (removal of offset already present on the analogue input signal H03M1/1295) · CPC title

• H03M1/002 Primary

  Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed · CPC title

• H03M1/804

  with charge redistribution · CPC title

• H03M1/164

  the steps being performed sequentially in series-connected stages (H03M1/161 takes precedence) · CPC title