Oxide-based resistive non-volatile memory cell and method for manufacturing same

Patent metadata

Field	Value
Publication number	US-11189792-B2
Application number	US-201716331714-A
Country	US
Kind code	B2
Filing date	Sep 8, 2017
Priority date	Sep 9, 2016
Publication date	Nov 30, 2021
Grant date	Nov 30, 2021

Abstract

A resistive non-volatile memory cell includes a first electrode, a second electrode and an oxide layer disposed between the first electrode and the second electrode, the memory cell being capable of reversibly switching between: —a high resistance state obtained by applying a first bias voltage between the first electrode and the second electrode; and—a low resistance state obtained by applying a second bias voltage between the first electrode and the second electrode; the oxide layer including a switching zone forming a conduction path prioritised for the current passing through the memory cell when the memory cell is in the low resistance state. The oxide layer includes a first zone doped with aluminium or silicon, the aluminium or silicon being present in the first zone with an atomic concentration that is selected so as to locate the switching zone outside the first zone.

First claim

The invention claimed is:

1. Resistive non-volatile memory cell comprising a first electrode, a second electrode and an oxide layer arranged between the first electrode and the second electrode, the memory cell being capable of reversibly switching between:
a high resistance state obtained by applying a first bias voltage between the first electrode and the second electrode; and
a low resistance state obtained by applying a second bias voltage between the first electrode and the second electrode;

the oxide layer comprising a unique switching zone forming a favored conduction path for the current passing through the memory cell when the memory cell is in the low resistance state, wherein the oxide layer comprises a first zone doped with aluminium or silicon, a difference of an atomic concentration of the alumunium or the silicon between the first zone and a second zone of the oxide layer outside the first zone being selected such that said difference by itself allows the unique switching zone to be located in said second zone outside the first zone, wherein the atomic concentration of the aluminium or the silicon in the first zone is greater than 0% and up to 5% and the atomic concentration of the aluminium or the silicon in the second zone is from 0% to 5%.

2. The memory cell according to claim 1 , wherein the first zone extends to a periphery of the memory cell.

3. The memory cell according to claim 1 , wherein the first zone is doped with silicon, the atomic concentration of silicon in the first zone being comprised between 0.1% and 2%.

4. The memory cell according to claim 3 , wherein the oxide layer comprises the second zone doped with silicon, the silicon being present in the second zone at the atomic concentration that is selected so as to locate the switching zone in the second zone.

5. The memory cell according to claim 4 , wherein the first zone completely surrounds the second zone.

6. The memory cell according to claim 4 , wherein the first zone comprises:
a first portion and a second portion extending on either side of the second zone along a first direction;
a third portion and a fourth portion extending on either side of the second zone along a second direction substantially orthogonal to the first direction.

7. The memory cell according to claim 1 , wherein the atomic concentration of silicon in the second zone is greater than 3% and up to 5%.

8. The memory cell according to claim 1 , wherein the oxide layer comprises a material among the following: hafnium oxide, tantalum oxide.

9. Method for manufacturing a resistive non-volatile memory cell-comprising a first electrode, a second electrode and an oxide layer arranged between the first electrode and the second electrode, the memory cell being capable of reversibly switching between:
a high resistance state obtained by applying a first bias voltage between the first electrode and the second electrode; and
a low resistance state obtained by applying a second bias voltage between the first electrode and the second electrode;

the oxide layer comprising a unique switching zone forming a favored conduction path for the current passing through the memory cell when the memory cell is in the low resistance state, the method further comprising forming in the oxide layer a first zone doped with aluminium or silicon, a difference of an atomic concentration of alumunium or silicon between the first zone and a second zone of the oxide layer outside the first zone being selected such that said difference by itself allows the unique switching zone to be located in said second zone outside the first zone, wherein the atomic concentration of the aluminium or the silicon in the first zone is greater than 0% and up to 5% and the atomic concentration of the aluminium or the silicon in the second zone is from 0% to 5%.

10. The method according to claim 9 , wherein the forming comprises a first step of ion implantation of aluminium or silicon in the first zone.

11. The method according to claim 9 , wherein the forming comprises a first step of ion implantation of silicon in a first region of the oxide layer and a second step of ion implantation of silicon in a second region of the oxide layer, the first region and the second region merging at least partially and forming:
the first zone of the oxide layer in which the first region and the second region are not merged; and
the second zone of the oxide layer in which the first region and the second region are merged;
after the first implantation step and the second implantation step are carried out, silicon is present in the second zone at the atomic concentration that is selected so as to locate the switching zone in the second zone.

12. The method according to claim 11 , wherein the first implantation step comprises a first operation of masking the oxide layer carried out in such a way that the first region forms a first trench extending along a first direction, and wherein the second implantation step comprises a second operation of masking the oxide layer carried out in such a way that the second region forms a second trench extending along a second direction substantially orthogonal to the first direction, the second trench crossing the first trench, the second zone being formed by the intersection of the first trench and the second trench.

13. The method according to claim 11 , further comprising depositing, on the oxide layer, an electrically conductive layer intended to form an electrode, the first implantation step and/or the second implantation step being carried out after the depositing of the electrically conductive layer.

Assignees

• Commissariat Energie Atomique

Inventors

• Grenouillet Laurent
• Barlas Marios
• Blaise Philippe
• Sklenard Benoît
• Vianello Elisa

Classifications

• H10N70/24

  based on migration or redistribution of ionic species, e.g. anions, vacancies · CPC title

• H01L45/1253

  Electricity · mapped topic

• H01L45/146

  Electricity · mapped topic

• H01L45/165 Primary

  Electricity · mapped topic

• H01L27/2472

  Electricity · mapped topic