Two-terminal memory compatibility with NAND flash memory set features type mechanisms

Patent metadata

Field	Value
Publication number	US-9727258-B1
Application number	US-201514642205-A
Country	US
Kind code	B1
Filing date	Mar 9, 2015
Priority date	Oct 3, 2014
Publication date	Aug 8, 2017
Grant date	Aug 8, 2017

Abstract

Operating characteristics associated with NAND flash memory can be modified and/or emulated to support corresponding operating characteristics for two-terminal memory. As a result, NAND flash memory modules included in conventional NAND flash memory devices (e.g., memory cards, solid-state drives, etc.) can be replaced with two-terminal memory without substantial changes to manufacturing infrastructure associated with the manufacture of these NAND flash memory devices.

First claim

What is claimed is:

1. A memory device, comprising:
one or more memory modules comprising an array of non-volatile two-terminal memory cells;
a memory command input interface; and
a module controller and translator (MCT) configured to:
activate or deactivate a NAND emulation mode in response to an activation command, wherein the NAND emulation mode, in response to a NAND flash memory command, performs a low-level memory operation on a subset of the non-volatile two-terminal memory cells that at least in part emulates a function associated with the NAND flash memory command; and
set a two-terminal memory operational characteristic for the one or more memory modules in response to a configuration command received over the memory command input interface for setting a NAND operational characteristic for NAND flash memory, wherein the configuration command relates to a Feature parameter that is set according to a Set Features command, and the Set Features command relates to an overwrite capability supported by the two-terminal memory cells, wherein the overwrite capability is characterized by updating a current state associated with a memory cell independently of the current state.

2. The memory device of claim 1 , wherein the configuration command is received from a host device over the memory command input interface.

3. The memory device of claim 1 , wherein the MCT is further configured to translate a low-level NAND flash memory data operation command to a corresponding low-level two-terminal memory data operation command.

4. The memory device of claim 3 , wherein the low-level NAND flash memory data operation command is a program page command or an erase block command and the corresponding low-level two-terminal memory data operation command is an overwrite command.

5. The memory device of claim 4 , wherein the overwrite command applies to at least one bit included in a page of memory defined by the program page command without overwriting other bits included in the page of memory, or included in a block of memory defined by the erase block command without overwriting other bits included in the block of memory.

6. The memory device of claim 1 , wherein the configuration command relates to a mode of operation for the NAND flash memory, wherein the mode of operation conforms to a defined set of NAND operational characteristics including the NAND operational characteristic.

7. The memory device of claim 1 , wherein the configuration command relates to at least one of timing characteristics, voltage characteristics, current characteristics, or other electrical characteristics.

8. The memory device of claim 1 , wherein the Set Features command further relates to a vendor specific Feature parameter.

9. The memory device of claim 1 , wherein the Set Features command further relates to a page erase capability supported by the two-terminal memory cells, wherein the page erase capability is characterized by setting two-terminal memory cells included in a logical page of memory to a defined state, wherein the defined state is associated with a specific bit value.

10. The memory device of claim 1 , wherein the MCT issues multiple page erase commands that emulates a NAND-based block erase command in response to the Set Features command being activated.

11. The memory device of claim 1 , wherein the Set Features command further relates to a configurable page size capability supported by the two-terminal memory cells.

12. The memory device of claim 1 , wherein the Set Features command further relates to a configurable garbage collection functionality.

13. The memory device of claim 1 , wherein the Set Features command further relates to a configurable error correcting code (ECC) functionality.

14. The memory device of claim 1 , wherein the Set Features command further relates to a configurable block management functionality.

15. The memory device of claim 1 , wherein the Set Features command further relates to a configurable multi-level cell (MLC) pagination functionality.

16. A method, comprising:
receiving, by a command interface, a configuration command for NAND flash memory;
identifying, by a memory controller, a setting associated with a NAND characteristic for controlling an operational characteristic of NAND flash memory related to the configuration command;
determining, by the memory controller, a corresponding setting associated with a two-terminal memory characteristic for controlling an operational characteristic of a two-terminal memory array; and
configuring, by the memory controller, a memory device that comprises the two-terminal memory array according to the corresponding setting and in response to the configuration command for NAND flash memory; and
configuring, by the memory controller, the memory device according to the corresponding setting, wherein the corresponding setting relates to an overwrite capability supported by the two-terminal memory array characterized by updating a current state of a cell of the two-terminal memory array independently of the current state.

17. The method of claim 16 , wherein the corresponding setting further relates to a sub-block erase capability characterized by erasing fewer bits than are defined for a block of memory.

18. The method of claim 16 , wherein the corresponding setting further relates to a configurable page size capability supported by the two-terminal memory array.

19. The method of claim 16 , wherein the corresponding setting further relates to a configurable garbage collection capability supported by the two-terminal memory array.

20. The method of claim 16 , further comprising:
receiving, by the memory controller, a low-level NAND flash memory data operation command;
translating, by the memory controller, the low-level NAND flash memory data operation command to a corresponding low-level two-terminal memory data operation command; and
issuing, by the memory controller, the corresponding low-level two-terminal memory data operation command to the two-terminal memory array.

21. The method of claim 20 , wherein the low-level NAND flash memory data operation command is a program page command and the corresponding low-level two-terminal memory data operation command comprises an instruction to overwrite a set of bits that is less than a number of bits defined by the program page command.

22. The method of claim 20 , wherein the low-level NAND flash memory data operation command is an erase block command and the corresponding low-level two-terminal memory data operation command comprises an instruction to overwrite a set of bits that is less than a number of bits defined by the erase block command.

23. A memory device, comprising:
one or more memory modules comprising an array of non-volatile two-terminal memory cells;
a memory command input interface; and
a module controller and translator (MCT) configured to:
activate or deactivate a NAND emulation mode in response to an activation command, wherein the NAND emulation mode, in response to a NAND flash memory command, performs a low-level memory operation on a subset of the non-volatile two-terminal memory cells that at least in part emulates a function associated with the NAND flash memory command; and
set a two-terminal memory operational characteristic for the one or more memory modules in response to a configuration command received over the memory command input interface for setting a NAND operational characteristic for NAND flash memory, wher

Assignees

• Crossbar Inc

Inventors

• Nazarian Hagop
• Kim Kuk-Hwan

Classifications

• G06F11/1048 Primary

  using arrangements adapted for a specific error detection or correction feature · CPC title

• G06F3/0659 Primary

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G06F3/0619 Primary

  in relation to data integrity, e.g. data losses, bit errors · CPC title

• G06F3/0688

  Non-volatile semiconductor memory arrays · CPC title

• G11C2213/75

  Array having a NAND structure comprising, for example, memory cells in series or memory elements in series, a memory element being a memory cell in parallel with an access transistor · CPC title