Time dependent dielectric breakdown test structure and test method thereof

Patent metadata

Field	Value
Publication number	US-11187740-B2
Application number	US-201816207178-A
Country	US
Kind code	B2
Filing date	Dec 2, 2018
Priority date	Nov 6, 2018
Publication date	Nov 30, 2021
Grant date	Nov 30, 2021

Abstract

A time dependent dielectric breakdown test structure includes a plurality of test units connected in parallel between a constant voltage and a ground. Each of the plurality of test units includes a dielectric test sample connected to the constant voltage; and a current restraint unit connected between the dielectric test sample and the ground, for restraining a breakdown current from flowing on the dielectric test sample after the constant voltage has broken the dielectric test sample.

First claim

What is claimed is:

1. A time dependent dielectric breakdown (TDDB) test structure, comprising:
a plurality of N-type test units connected in parallel between a constant voltage and a ground, wherein the constant voltage is positive and each of the plurality of N-type test units comprises:
a dielectric test sample connected to the constant voltage;
a current restraint circuit, comprising:
at least one depleted field effect (DEPFET) transistor comprising a drain connected to the dielectric test sample, a gate connected to the ground, a base connected to the ground, and a source, configured to restrain a breakdown current from flowing on the dielectric test sample after the constant voltage has broken the dielectric test sample; and
a resistor connected between the source of the at least one DEPFET transistor and the ground;

wherein the dielectric test sample is still directly connected to the constant voltage after the constant voltage has broken the dielectric test sample;
wherein a cross voltage of the resistor caused by the breakdown current is greater than an absolute of a total threshold voltage of the at least one DEPFET transistor.

2. The TDDB test structure of claim 1 , wherein when the constant voltage breaks the dielectric test sample, the cross voltage of the resistor causes a total gate-to-source voltage of the at least one DEPFET transistor less than the total threshold voltage to turn off the at least one DEPFET transistor, to restrain the breakdown current from flowing on the dielectric test sample.

3. A time dependent dielectric breakdown (TDDB) test structure, comprising:
a plurality of P-type test units connected in parallel between a constant voltage and a ground, wherein the constant voltage is negative and each of the plurality of P-type test units comprises:
a dielectric test sample connected to the constant voltage; and
a current restraint circuit comprising:
at least one depleted field effect (DEPFET) transistor comprising a drain connected to the ground, a source, a gate connected to the dielectric test sample, and a base connected to the dielectric test sample, configured to restrain a breakdown current from flowing on the dielectric test sample after the constant voltage has broken the dielectric test sample; and
a resistor connected between the source of the at least one DEPFET transistor and the dielectric test sample;

wherein the dielectric test sample is still directly connected to the constant voltage after the constant voltage has broken the dielectric test sample;
wherein a cross voltage of the resistor caused by the breakdown current is greater than an absolute of a total threshold voltage of the at least one DEPFET transistor.

4. The TDDB test structure of claim 3 , wherein when the constant voltage breaks the dielectric test sample, the cross voltage of the resistor causes a total gate-to-source voltage of the at least one DEPFET transistor less than the total threshold voltage to turn off the at least one DEPFET transistor, to restrain the breakdown current from flowing on the dielectric test sample.

5. A time dependent dielectric breakdown (TDDB) test method, comprising:
connecting a plurality of test units in parallel between a constant voltage and a ground; and
measuring a current-time curve between the constant voltage and the ground to read a plurality of breakdown times corresponding to the plurality of test units;
wherein the plurality of test units comprises a plurality of dielectric test samples, and one of the plurality of dielectric test samples is still directly connected to the constant voltage after the constant voltage has broken the one of the plurality of dielectric test samples;
wherein each of the plurality of test units comprises at least one depleted field effect (DEPFET) transistor;
wherein the plurality of test units are a plurality of N-type test units or a plurality of P-type test units; and
wherein the plurality of N-type test unit connected in parallel between a constant voltage and a ground, wherein the constant voltage is positive and each of the plurality of N-type test units comprises a dielectric test sample connected to the constant voltage;
a current restraint circuit, comprising:
at least one depleted field effect (DEPFET) transistor comprising a drain connected to the dielectric test sample, a gate connected to the ground, a base connected to the ground, and a source, configured to restrain a breakdown current from flowing on the dielectric test sample after the constant voltage has broken the dielectric test sample; and

a resistor connected between the source of the at least one DEPFET transistor and the ground; and

wherein the plurality of P-type test units are a plurality connected in parallel between a constant voltage and a ground, wherein the constant voltage is negative and each of the plurality of P-type test units comprises:
a dielectric test sample connected to the constant voltage; and
a current restraint circuit comprising:
at least one depleted field effect (DEPFET) transistor comprising a drain connected to the ground, a source, a gate connected to the dielectric test sample, and a base connected to the dielectric test sample, configured to restrain a breakdown current from flowing on the dielectric test sample after the constant voltage has broken the dielectric test sample; and

a resistor connected between the source of the at least one DEPFET transistor and the dielectric test sample.

6. The TDDB test method of claim 5 , wherein the method further comprises:
restraining one of a plurality of breakdown currents from flowing on one of the plurality of dielectric test samples after the constant voltage has broken the one of the plurality of dielectric test samples.

7. The TDDB test method of claim 6 , the at least one DEPFET transistor is turned off after the constant voltage has broken one of the plurality of dielectric test samples, to restrain the breakdown current from flowing on one of the plurality of dielectric test samples.

Assignees

• Yangtze Memory Tech Co Ltd

Inventors

• Yang Shengwei
• Han Kun

Classifications

• H10P74/277

  Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers · CPC title

• H10P74/207

  Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics · CPC title

• G01R31/1263 Primary

  of solid or fluid materials, e.g. insulation films, bulk material; of semiconductors or LV electronic components or parts; of cable, line or wire insulation · CPC title

• G01R31/129

  of components or parts made of semiconducting materials; of LV components or parts (G01R31/18 takes precedence) · CPC title

• G01R31/14 Primary

  Circuits therefor {, e.g. for generating test voltages, sensing circuits (G01R31/1209 - G01R31/1227 take precedence; for testing switches G01R31/327)} · CPC title