Method for processing a layer structure and microelectromechanical component

Patent metadata

Field	Value
Publication number	US-11180362-B2
Application number	US-202016878161-A
Country	US
Kind code	B2
Filing date	May 19, 2020
Priority date	Sep 4, 2017
Publication date	Nov 23, 2021
Grant date	Nov 23, 2021

Abstract

In accordance with various embodiments, a method for processing a layer structure is provided, where the layer structure includes a first layer, a sacrificial layer arranged above the first layer, and a second layer arranged above the sacrificial layer, where the second layer includes at least one opening, and the at least one opening extends from a first side of the second layer as far as the sacrificial layer. The method includes forming a liner layer covering at least one inner wall of the at least one opening; forming a cover layer above the liner layer, where the cover layer extends at least in sections into the at least one opening; and wet-chemically etching the cover layer, the liner layer and the sacrificial layer using an etching solution, where the etching solution has a greater etching rate for the liner layer than for the cover layer.

First claim

What is claimed is:

1. A microelectromechanical component, comprising:
a first layer and a second layer arranged above the first layer, wherein a cavity is provided between the first layer and the second layer, and wherein the second layer comprises a contacting region;
a liner layer arranged in the contacting region above the second layer, wherein the liner layer comprises an undoped oxidic material and wherein the liner layer has a layer thickness of less than 50 nm;
a cover layer arranged in the contacting region above the liner layer, wherein the cover layer comprises a doped oxidic material and wherein the cover layer has a greater layer thickness than the liner layer;
wherein a contact hole extends through the liner layer and the cover layer as far as the second layer to contact a surface section of the second layer;
an electrically conductive diffusion barrier layer, which covers the cover layer, a sidewall of the contact hole and the surface section of the second layer; and
a metal layer arranged above the diffusion barrier layer to contact the second layer in the contacting region.

2. The microelectromechanical component as claimed in claim 1 , wherein the liner layer comprises undoped silicon oxide, and wherein the cover layer comprises doped silicon oxide.

3. The microelectromechanical component as claimed in claim 1 , wherein the cover layer comprises silicon oxide which is doped with phosphorus or which is doped with boron and phosphorus.

4. The microelectromechanical component as claimed in claim 1 , wherein the first layer comprises a semiconducting material, or wherein the second layer comprises the semiconducting material.

5. The microelectromechanical component as claimed in claim 1 , wherein a surface section of the first layer and a surface section of the second layer are exposed outside the contacting region.

6. The microelectromechanical component as claimed in claim 1 , wherein the liner layer has a layer thickness of more than 5 nm, and wherein the cover layer has a layer thickness in a range of 100 nm to 20 μm.

7. The microelectromechanical component as claimed in claim 1 , wherein the cover layer comprises a beveled cover layer.

8. A method of fabricating a microelectromechanical component, the method comprising:
arranging a first layer and a second layer above the first layer, wherein a cavity is provided between the first layer and the second layer, and wherein the second layer comprises a contacting region;
arranging a liner layer in the contacting region above the second layer, wherein the liner layer comprises an undoped oxidic material and wherein the liner layer has a layer thickness of less than 50 nm;
arranging a cover layer in the contacting region above the liner layer, wherein the cover layer comprises a doped oxidic material and wherein the cover layer has a greater layer thickness than the liner layer;
extending a contact hole through the liner layer and the cover layer as far as the second layer to contact a surface section of the second layer;
providing an electrically conductive diffusion barrier layer, which covers the cover layer, a sidewall of the contact hole and the surface section of the second layer; and
arranging a metal layer above the diffusion barrier layer to contact the second layer in the contacting region.

9. The method as claimed in claim 8 , wherein the liner layer comprises undoped silicon oxide, and wherein the cover layer comprises doped silicon oxide.

10. The method as claimed in claim 8 , wherein the cover layer comprises silicon oxide which is doped with phosphorus or which is doped with boron and phosphorus.

11. The method as claimed in claim 8 , wherein the first layer comprises a semiconducting material, or wherein the second layer comprises the semiconducting material.

12. The method as claimed in claim 8 , wherein a surface section of the first layer and a surface section of the second layer are exposed outside the contacting region.

13. The method as claimed in claim 8 , wherein the liner layer has a layer thickness of more than 5 nm, and wherein the cover layer has a layer thickness in a range of 100 nm to 20 μm.

14. The method as claimed in claim 8 , wherein the cover layer comprises a beveled cover layer.

Assignees

• Infineon Technologies Ag

Inventors

• Brockmeier Andre
• Friza Wolfgang
• Maurer Daniel

Classifications

• B81C1/00476 Primary

  removing a sacrificial layer (B81C1/00912 takes precedence) · CPC title

• B81C1/00047 Primary

  Cavities · CPC title

• B81C1/00595

  Control etch selectivity · CPC title

• B81B7/02

  containing distinct electrical or optical devices of particular relevance for their function, e.g. microelectro-mechanical systems [MEMS] (B81B7/04 takes precedence) · CPC title

• B81C1/00571

  Avoid or control under-cutting · CPC title