Method and system for pattern configuration

Patent metadata

Field	Value
Publication number	US-11176307-B2
Application number	US-201716349317-A
Country	US
Kind code	B2
Filing date	Nov 13, 2017
Priority date	Dec 1, 2016
Publication date	Nov 16, 2021
Grant date	Nov 16, 2021

Abstract

A method including: obtaining a device design pattern layout having a plurality of design pattern polygons; automatically identifying, by a computer, a unit cell of polygons in the device design pattern layout; identifying a plurality of occurrences of the unit cell within the device design pattern layout to build a hierarchy; and performing, by the computer, an optical proximity correction on the device design pattern layout by repeatedly applying an optical proximity correction designed for the unit cell to the occurrences of the unit cell in the hierarchy.

First claim

The invention claimed is:

1. A method, comprising:
obtaining a device design pattern layout comprising a plurality of design pattern polygons;
performing automatic pattern recognition, by a hardware computer, of a unit cell of polygons in the device design pattern layout;
searching for previously unidentified occurrences of the unit cell within the device design pattern layout to build a hierarchy; and
performing, by the computer, an optical proximity correction on the device design pattern layout by repeatedly applying an optical proximity correction designed for the unit cell to the occurrences of the unit cell in the hierarchy.

2. The method of claim 1 , wherein the unit cell is specified such that polygons within the unit cell have symmetry with respect to at least one axis through the unit cell.

3. The method of claim 1 , further comprising receiving a specification of a sub-region of the device design pattern layout in which to recognize the unit cell and identifying the plurality of occurrences of the unit cell comprises identifying an occurrence of the unit cell in the device design pattern layout outside of the sub-region.

4. The method of claim 1 , wherein the unit cell is recognized by tracking a plurality of pitches between polygons.

5. The method of claim 1 , wherein, prior to performing automatic pattern recognition of the unit cell, the device design pattern layout does not have an available hierarchy.

6. The method of claim 1 , wherein no prior hierarchy information is used to create the hierarchy.

7. A computer program product comprising a non-transitory computer-readable medium having instructions recorded thereon, the instructions, upon execution by a computer system, configured to cause the computer system to at least:
obtain a device design pattern layout comprising a plurality of design pattern polygons;
perform automatic pattern recognition, by a hardware computer, of a unit cell of polygons in the device design pattern layout;
search for previously unidentified a plurality of occurrences of the unit cell within the device design pattern layout; and
build a hierarchy based on the identified plurality of occurrences, the hierarchy designed for use in an optical proximity correction of the device design pattern layout.

8. A computer program product comprising a non-transitory computer-readable medium having instructions recorded thereon, the instructions, upon execution by a computer system, configured to cause the computer system to at least:
obtain a device design pattern layout comprising a plurality of design pattern polygons;
perform automatic pattern recognition of a unit cell of polygons in the device design pattern layout;
search for previously unidentified occurrences of the unit cell within the device design pattern layout to build a hierarchy; and
perform an optical proximity correction on the device design pattern layout by repeatedly applying an optical proximity correction designed for the unit cell to the occurrences of the unit cell in the hierarchy.

9. The computer program product of claim 8 , wherein the unit cell is a minimum sized unit cell in the device design pattern layout.

10. The computer program product of claim 8 , wherein the unit cell is specified such that the boundary of the unit cell does not pass through any polygons.

11. The computer program product of claim 8 , wherein the unit cell is specified such that it can be tessellated within a region of the device design pattern layout.

12. The computer program product of claim 8 , wherein the unit cell is specified such that polygons within the unit cell have symmetry with respect to at least one axis through the unit cell.

13. The computer program product of claim 8 , wherein the instructions are further configured to cause the computer system to perform an optical proximity correction on the unit cell to create the optical proximity correction designed for the unit cell.

14. The computer program product of claim 8 , wherein the instructions are further configured to cause the computer system to automatically identify a region of repeating sets of polygons from the device design pattern layout and wherein the automatic pattern recognition comprises evaluation of the region of the repeating sets of polygons to determine the unit cell.

15. The computer program product of claim 8 , wherein the hierarchy comprises an identification of the unit cell (or of structures corresponding to the unit cell), a specification of the number of instances of the unit cell (or of the structures corresponding to the unit cell) in at least a portion of the device design pattern layout, and a locational identification of the instances (or of the structures corresponding to the unit cell) in the at least portion of the device design pattern layout.

16. The computer program product of claim 8 , wherein the instructions are further configured to cause the computer system to perform an optical proximity correction on the unit cell to create the optical proximity correction designed for the unit cell.

17. The computer program product of claim 8 , wherein the device design pattern layout corresponds to a memory device and the unit cell corresponds to polygons for a cell or bank of the memory device.

18. The computer program product of claim 8 , wherein the instructions are further configured to cause the computer system to recognize the unit cell by tracking a plurality of pitches between polygons.

19. The computer program product of claim 8 , wherein, prior the automatic pattern recognition of the unit cell, the device design pattern layout does not have an available hierarchy.

20. The computer program product of claim 8 , wherein no prior hierarchy information is used to create the hierarchy.

Assignees

• Asml Netherlands Bv

Inventors

• Vellanki Venugopal
• Chen Been-Der

Classifications

• G03F7/70441 Primary

  Optical proximity correction [OPC] · CPC title

• G06F30/398 Primary

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G03F1/36

  Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes · CPC title

• G06F30/392

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• H10P76/00

  Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography · CPC title