Per chiplet thermal control in a disaggregated multi-chiplet system

Patent metadata

Field	Value
Publication number	US-11175709-B2
Application number	US-201916551523-A
Country	US
Kind code	B2
Filing date	Aug 26, 2019
Priority date	Aug 26, 2019
Publication date	Nov 16, 2021
Grant date	Nov 16, 2021

Abstract

Particular embodiments described herein provide for an electronic device that can be configured to include a plurality of chiplets, a plurality of resources, a system thermal engine, and at least one processor. The at least one processor is configured to cause the system thermal engine to monitor the plurality of chiplets, where the plurality of chiplets are part of a multi-chip module, determine that a first chiplet from the plurality of chiplets has reached a threshold temperature, and reduce power to the first chiplet without reducing power to the other chiplets in the plurality of chiplets.

First claim

What is claimed is:

1. An electronic device comprising:
a plurality of chiplets that are part of a multi-chip module, wherein at least two of the plurality of chiplets have different clock rates and at least one of the plurality of chiplets includes a plurality of cores;
at least one processor, wherein the at least one processor is configured to
monitor the plurality of chiplets;
determine that a first chiplet from the plurality of chiplets has reached a threshold temperature;
reduce power to the first chiplet without reducing power to other chiplets in the plurality of chiplets;
monitor one or more resources to be used by the plurality of chiplets during execution of a workload;
determine that a third chiplet from the plurality of chiplets will consume one or more resources needed by a second chiplet during execution of the workload; and
reduce voltage to the third chiplet without reducing voltage to the other chiplets in the plurality of chiplets, wherein the voltage reduction to the third chiplet causes the third chiplet to not consume an amount of the one or more resources that is needed by the second chiplet during execution of the workload.

2. The electronic device of claim 1 , further comprising a first chiplet thermal engine, wherein the first chiplet thermal engine communicates a clock frequency value to a system thermal engine that will allow the first chiplet to operate without further exceeding the threshold temperature.

3. The electronic device of claim 1 , wherein the threshold temperature is a thermal limit of the first chiplet and the threshold temperature is different than a thermal limit of a second chiplet from the plurality of chiplets.

4. The electronic device of claim 1 , wherein the first chiplet is a logic chiplet.

5. The electronic device of claim 1 , wherein the at least one processor is further configured to cause a system thermal engine to:
determine that a second chiplet from the plurality of chiplets has reached a threshold temperature; and
reduce power to the second chiplet without reducing power to the other chiplets in the plurality of chiplets.

6. At least one non-transitory machine readable medium comprising one or more instructions that, when executed by at least one processor, causes the at least one processor to:
determine a workload to be executed by a plurality of chiplets, wherein the plurality of chiplets are part of a multi-chip module, wherein one or more of the plurality of chiplets includes a plurality of cores and at least two of the plurality of chiplets have different clock rates;
monitor the plurality of chiplets and one or more resources to be used by the plurality of chiplets during execution of the workload;
determine that a first chiplet from the plurality of chiplets has reached a threshold temperature;
reduce power to the first chiplet without reducing power to other chiplets in the plurality of chiplets;
determine that a third chiplet from the plurality of chiplets will consume one or more resources needed by a second chiplet during execution of the workload; and
reduce voltage to the third chiplet without reducing voltage to the other chiplets in the plurality of chiplets, wherein the voltage reduction to the third chiplet causes the third chiplet to not consume an amount of the one or more resources that is needed by the second chiplet during execution of the workload.

7. The at least one machine readable medium of claim 6 , wherein one of the one or more resources needed by the second chiplet during execution of the workload is a power supply resource.

8. The at least one machine readable medium of claim 6 , wherein the one or more instructions further cause the at least one processor to:
determine that a third chiplet from the plurality of chiplets has reached a threshold temperature; and
reduce power to the third chiplet without reducing power to the other chiplets in the plurality of chiplets.

9. The at least one machine readable medium of claim 6 , wherein the first chiplet is a logic chiplet.

10. The at least one machine readable medium of claim 9 , wherein the second chiplet is a graphics chiplet.

11. A system for enabling thermal control of a chiplet in a disaggregated multi-chiplet system, the system comprising:
memory;
a plurality of chiplets, wherein the plurality of chiplets are part of a multi-chip module and at least two of the plurality of chiplets have different clock rates; and
a system thermal engine, wherein the system thermal engine is configured to:
determine a workload to be executed by the plurality of chiplets;
monitor the plurality of chiplets;
determine that a first chiplet from the plurality of chiplets has reached a threshold temperature;
reduce voltage to the first chiplet without reducing voltage to other chiplets in the plurality of chiplets;
monitor one or more resources to be used by the plurality of chiplets during execution of the workload;
determine that a third chiplet from the plurality of chiplets will consume one or more resources needed by a second chiplet during execution of the workload; and
reduce voltage to the third chiplet without reducing voltage to the other chiplets in the plurality of chiplets, wherein the voltage reduction to the third chiplet causes the third chiplet to not consume an amount of the one or more resources that is needed by the second chiplet during execution of the workload.

12. The system of claim 11 , wherein the first chiplet includes a first chiplet thermal engine, wherein the first chiplet thermal engine communicates a clock frequency value to the system thermal engine that will allow the first chiplet to operate without further reaching the threshold temperature.

13. The system of claim 11 , wherein the first chiplet is a logic chiplet and a second chiplet is a graphics chiplet.

14. The system of claim 11 , wherein the system thermal engine is further configured to:
determine that a second chiplet from the plurality of chiplets has reached a threshold temperature; and
reduce voltage to the second chiplet without reducing power to the other chiplets in the plurality of chiplets.

15. A method comprising:
monitoring a first chiplet and a second chiplet, wherein the first chiplet and the second chiplet are part of a multi-chip module that includes a plurality of chiplets, wherein at least one chiplet from the plurality of chiplets has a clock rate that is different from other chiplets in the plurality of chiplets and one or more of the plurality of chiplets includes a plurality of cores;
determining that the first chiplet has reached a threshold temperature;
reducing power to the first chiplet without reducing power to the second chiplet;
monitoring one or more resources to be used by the plurality of chiplets during execution of a workload;
determining that a third chiplet from the plurality of chiplets will consume one or more resources needed by a second chiplet during execution of the workload; and
reducing voltage to the third chiplet without reducing voltage to the other chiplets in the plurality of chiplets, wherein the voltage reduction to the third chiplet causes the third chiplet to not consume an amount of the one or more resources that is needed by the second chiplet during execution of the workload.

16. The method of claim 15 , wherein the first chiplet is a logic chiplet and the second chiplet is a graphics chiplet.

17. The method of claim 15 , wherein the first chiplet includes a first chiplet thermal engine, wherein the first chiplet thermal engine communicates a clock frequency value to

Assignees

• Intel Corp

Inventors

• Jain Amit Kumar
• Shekhar Sameer
• Carbone Mark
• Brown Merwin M

Classifications

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• G06F11/3058 Primary

  Monitoring arrangements for monitoring environmental properties or parameters of the computing system or of the computing system component, e.g. monitoring of power, currents, temperature, humidity, position, vibrations (thermal management in cooling arrangements of a computing system G06F1/206) · CPC title

• G06F1/08

  Clock generators with changeable or programmable clock frequency · CPC title

• G06F1/324

  by lowering clock frequency · CPC title

• G06F1/28

  Supervision thereof, e.g. detecting power-supply failure by out of limits supervision · CPC title