Integrated circuit package substrate

Patent metadata

Field	Value
Publication number	US-11166379-B2
Application number	US-201916504842-A
Country	US
Kind code	B2
Filing date	Jul 8, 2019
Priority date	Apr 25, 2013
Publication date	Nov 2, 2021
Grant date	Nov 2, 2021

Abstract

Embodiments of the present disclosure are directed towards techniques and configurations for dual surface finish package substrate assemblies. In one embodiment a method includes depositing a first surface finish on one or more electrical routing features located on a first side of a package substrate and on one or more lands located on a second side of the package substrate, the second side being opposite the first side of the substrate. The method may further include removing the first surface finish on the first side of the package substrate; and depositing a second surface finish on the one or more electrical routing features of the first side. The depositing of the second surface finish may be accomplished by one of a Direct Immersion Gold (DIG) process or an Organic Solderability Preservative (OSP) process. Other embodiments may be described and/or claimed.

First claim

What is claimed is:

1. A package assembly comprising:
a die having one or more interconnect structures; and
a package substrate electrically coupled with the die, wherein the package substrate includes:
a first side including one or more lands, the one or more lands having a first surface finish disposed on the one or more lands;
a second side disposed opposite to the first side, wherein the second side includes an outer dielectric layer that has an outer surface, wherein the outer surface is an outer surface of the package substrate; and
one or more electrical routing features disposed in, and extending through, the outer dielectric layer, wherein the one or more electrical routing features have an outer surface that is coplanar with the outer surface of the outer dielectric layer, and having a second surface finish disposed on, and in direct contact with, the outer surface of the one or more electrical routing features, wherein the one or more electrical routing features have a pitch to bond with the one or more interconnect structures of the die, wherein the second surface finish has a different chemical composition than the first surface finish, wherein a bump pitch of the electrical routing features is 50 micrometers, and wherein the electrical routing features include a pad size of 49 micrometers, and wherein the second surface finish is affixed to the one or more interconnect structures.

2. The package assembly of claim 1 , wherein the die is a processor.

3. The package assembly of claim 1 , further comprising one or more of an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, a Geiger counter, an accelerometer, a gyroscope, a speaker, or a camera, wherein the package assembly is part of a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder.

Assignees

• Intel Corp

Inventors

• Zhang Qinglei

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/07236

  Soldering or alloying · CPC title

• H10W72/252

  comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/241

  Dispositions, e.g. layouts · CPC title

• H10W72/072

  of bump connectors · CPC title