Electrical node, method for manufacturing electrical node and multilayer structure comprising electrical node

Patent metadata

Field	Value
Publication number	US-11166364-B2
Application number	US-202016833744-A
Country	US
Kind code	B2
Filing date	Mar 30, 2020
Priority date	Jan 11, 2019
Publication date	Nov 2, 2021
Grant date	Nov 2, 2021

Abstract

An electrical node includes a substrate for accommodating a functional element. The substrate includes a first side and an opposite second side, and hosting a number of connecting elements. The functional element includes an electronic component and conductive traces. The electrical node also includes a first material layer defining a protective covering. The first material layer defining at least a portion of the exterior surface of the nod arranged to reduce at least thermal expansion and/or mechanical deformation related stresses between one or more elements included in the node, adjacent the node and/or at least at a proximity thereto.

First claim

The invention claimed is:

1. A multilayer structure comprising:
at least one electrical node including:
a substrate for accommodating at least one functional element, the substrate having a first side and an opposite second side, the at least one functional element including at least one electronic component and at least one conductive trace connected thereto, the at least one functional element provided to the substrate and projecting from the first side of the substrate;
at least one material layer forming a protective covering at least upon the at least one functional element, the first side of the substrate, and opposing first and second lateral sides of the substrate, the at least one material layer including elastic material and being arranged to reduce at least one of thermal expansion or mechanical deformation related stresses between one or more elements included in the at least one electrical node, adjacent the at least one electrical node, or at least at a proximity thereto; and
a thermal management element extending through an opening of the substrate and having a first portion disposed at the first side of the substrate and covered by the at least one material layer of the at least one electrical node, and a second portion disposed at the second side of the substrate; and an external structure including:
a host substrate supporting the at least one electrical node thereon; and
a plastic material layer produced on the host substrate and the at least one electrical node, thereby at least partially embedding at least the at least one material layer of the at least one electrical node therein.

2. The multilayer structure according to claim 1 , wherein the host substrate abuts the second side of the substrate.

3. The multilayer structure according to claim 1 , wherein the host substrate is connected to the second side of the substrate.

4. The multilayer structure according to claim 1 , wherein the at least one material layer is disposed on the first side of the substrate without covering the second side of the substrate.

5. The multilayer structure of claim 1 , wherein the substrate defines a recess or hole accommodating at least a portion of the at least one functional element.

6. The multilayer structure of claim 1 , wherein the at least one material layer has a coefficient of thermal expansion falling in a range between about 1 and 300 ppm/K.

7. The multilayer structure of claim 1 , wherein the at least one material layer is thermally conductive.

8. The multilayer structure of claim 1 , wherein the at least one material layer is at least one of transparent or colorless.

9. The multilayer structure of claim 1 , wherein the thermal management element is in thermal communication with the at least one electrical node.

10. The multilayer structure of claim 1 , wherein the at least one material layer includes a first material layer and a second material layer.

11. The multilayer structure according to claim 2 , wherein the at least one material layer is disposed on the first side of the substrate.

12. The multilayer structure of claim 5 , wherein the recess or hole of the substrate further accommodates at least a portion of the at least one material layer.

13. The multilayer structure of claim 9 , wherein the thermal management element includes at least one of a cooling element or a heating element.

14. The multilayer structure of claim 10 , wherein the first and second material layers are fabricated from a different material.

15. A method for manufacturing a multilayer structure, the method comprising:
obtaining a substrate having a first side and an opposite second side, at least one functional element being coupled to the substrate; and
providing at least one material layer in a pre-solidified state upon the at least one functional element and upon opposing first and second lateral sides of the substrate and at least a portion of the first side of the substrate to establish an integrated electrical node that includes the substrate, the at least one functional element, and the at least one material layer,
a thermal management element having a first portion covered by the at least one material layer of the at least one electrical node, and a second portion disposed externally of the at least one material layer, the thermal management element extending through an opening the substrate such that the first portion of the thermal management element is disposed at the first side of the substrate and the second portion of the thermal management element is disposed at the second side of the substrate;
attaching the integrated electrical node to a host substrate of an external structure; and
producing a plastic material layer upon the integrated electrical node and the host substrate, thereby at least partially embedding at least the at least one material layer of the integrated electrical node therein, wherein the plastic material layer is transparent.

16. The method of claim 15 , wherein the at least one material layer, in a solidified state, includes an elastic material arranged to reduce mechanical deformation related stresses between one or more elements included in the integrated electrical node, adjacent the integrated electrical node, or at least at a proximity thereto.

17. The method of claim 15 , wherein the plastic material layer is produced directly upon the integrated electrical node and the host substrate.

18. The method of claim 15 , wherein the at least one material layer is disposed on the first side of the substrate and the host substrate is disposed on the second side of the substrate.

19. The method of claim 16 , further comprising providing a second substrate to a side of the at least one material layer that is substantially opposite to a side facing the substrate.

Assignees

• Tactotek Oy

Inventors

• Keränen Antti
• Simula Tomi
• Heikkinen Mikko
• Sääski Jarmo
• Raappana Pasi
• Pirkonen Minna

Classifications

• H05K1/181

  associated with surface mounted components · CPC title

• H05K2201/10121

  Optical component, e.g. opto-electronic component · CPC title

• H05K1/0274

  Optical details, e.g. printed circuits comprising integral optical means (H05K1/0269 takes precedence; coupling light guides with opto-electronic components G02B6/42) · CPC title

• H05K2201/0129

  Thermoplastic polymer, e.g. auto-adhesive layer; Shaping of thermoplastic polymer · CPC title

• H05K1/185

  associated with components encapsulated in the insulating substrate of the PCBs; associated with components incorporated in internal layers of multilayer circuit boards · CPC title