Spin hall write select for magneto-resistive random access memory

Patent metadata

Field	Value
Publication number	US-11164615-B2
Application number	US-201815922333-A
Country	US
Kind code	B2
Filing date	Mar 15, 2018
Priority date	Feb 23, 2017
Publication date	Nov 2, 2021
Grant date	Nov 2, 2021

Abstract

A magneto-resistance random access memory (MRAM) cell includes a transistor, a wire and a magnetic tunnel junction (MTJ). The MTJ includes a fixed layer of fixed magnetic polarity electrically connected with the transistor, a free layer of variable magnetic polarity electrically connected with the wire and an insulator between the fixed and free layers. First current passed through the wire destabilizes the variable magnetic polarity of the free layer. Second current passed through the transistor in one of two directions during first current passage through the wire directs the variable magnetic polarity of the free layer toward a parallel or anti-parallel condition with respect to the fixed magnetic polarity of the fixed layer. A ceasing of the first current prior to a ceasing of the second current sets the variable magnetic polarity of the free layer in the parallel or anti-parallel condition.

First claim

What is claimed is:

1. A magneto-resistance random access memory (MRAM) device, comprising:
a wire;
a plurality of magnetic tunnel junctions (MTJs);
a substrate comprising an interior layer, a plurality of metallic landing pads and dielectric material portions disposed along the edge of the interior layer, surrounding sides of each metallic landing pad and comprising exterior facing surfaces, each metallic landing pad comprising:
a first surface recessed from the exterior facing surfaces and facing and abutting dielectric material of the interior layer of the substrate; and
a second surface opposite the first surface and coplanar with the exterior facing surfaces of the dielectric material portions;

a plurality of transistors disposed entirely within the interior layer of the substrate, each transistor being coupled, at the edge of the interior layer, to the first surface of a corresponding one of the plurality of the metallic landing pads through the dielectric material of the interior layer of the substrate by a connection which is narrower than the metallic landing pad and which extends from the transistor to the metallic landing pad through the dielectric material of the interior layer;
each of the plurality of the MTJs being respectively electrically connected between the wire and corresponding ones of the plurality of metallic landing pads and the plurality of transistors; and
a controller disposed within the interior layer of the substrate and coupled to the wire and the plurality of transistors and to respective supplies of first and second currents,
wherein:
the controller is configured to sequentially pass and cease first and second currents through the wire and the plurality of transistors, respectively, to set variable magnetic polarities of respective free layers of the plurality of MTJs in parallel or anti-parallel conditions with respect to fixed magnetic polarities of respective fixed layers of the plurality of MTJs, and
the transistors and the MTJs are arranged in a matrix with multiple rows and multiple columns and the wire is provided as a single wire with a serpentine configuration arranged throughout the matrix.

2. The MRAM device according to claim 1 , wherein the wire comprises metal or a metallic alloy.

3. The MRAM device according to claim 1 , wherein the wire comprises at least one of tungsten and tantalum.

4. The MRAM device according to claim 1 , wherein the first current exceeds the second current.

5. The MRAM device according to claim 1 , wherein the second current is initiated and ceased about 5-10 ns or less after the first current is initiated and ceased, respectively.

Assignees

• IBM

Inventors

• Liu Luqiao
• Sun Jonathan Z
• Worledge Daniel C

Classifications

• G11C11/1693

  Timing circuits or methods · CPC title

• G11C11/18

  using Hall-effect devices · CPC title

• G11C11/1675 Primary

  Writing or programming circuits or methods · CPC title

• G11C11/161

  details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell · CPC title

• G11C11/1659

  Cell access · CPC title