Semiconductor device with a passivation layer and method for producing thereof

Patent metadata

Field	Value
Publication number	US-11158557-B2
Application number	US-201916394803-A
Country	US
Kind code	B2
Filing date	Apr 25, 2019
Priority date	Mar 7, 2014
Publication date	Oct 26, 2021
Grant date	Oct 26, 2021

Abstract

A semiconductor device includes a semiconductor body comprising a first surface and an edge surface, a contact electrode formed on the first surface and comprising an outer edge side, and a passivation layer section conformally covering the outer edge side of the contact electrode. The passivation layer section is a multi-layer stack comprising a first layer, a second layer, and a third layer. Each of the first, second and third layers comprise outer edge sides facing the edge surface and opposite facing inner edge sides. The outer edge side of the contact electrode is disposed laterally between the inner edge sides and the outer edge sides of each layer. The inner and outer edge sides of the third layer are closer to the outer edge side of the electrode than the respective inner and outer edge sides of the first and second layer.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a semiconductor body comprising a first surface and an edge surface laterally terminating the first surface;
a contact electrode formed on the first surface and comprising an outer edge side that faces and is laterally spaced apart from the edge surface; and
a passivation layer section conformally covering the outer edge side of the contact electrode,
wherein the passivation layer section is a multi-layer stack comprising a first layer, a second layer, and a third layer, each of the first, second and third layers being formed from different electrically insulating materials,
wherein the first layer directly contacts the contact electrode and the first surface,
wherein the second layer is formed directly on the first layer,
wherein the third layer is formed directly on the second layer,
wherein each of the first, second and third layers comprise outer edge sides facing the edge surface of the semiconductor body and inner edge sides opposite from the outer edge sides,
wherein the outer edge side of the contact electrode extends along a first plane that is transverse to the first surface and wherein the first plane is disposed laterally between the inner edge sides and the outer edge sides of each of the first, second and third layers,
wherein the inner edge side of the third layer is laterally closer to the first plane than the inner edge side of the second layer is to the first plane, and
wherein the outer edge side of the third layer is laterally closer to the first plane than the outer edge side of the second layer is to the first plane.

2. The semiconductor device of claim 1 ,
wherein the edge surface of the semiconductor body extends along a second plane that is transverse to the first surface,
wherein the outer edge sides of each of the first, second and third layers are disposed laterally between the first plane and the second plane.

3. The semiconductor device of claim 1 ,
wherein inner edge sides of the first and second layers are laterally aligned with one another, and
wherein the outer edge sides of the first and second layers are laterally aligned with one another.

4. The semiconductor device of claim 1 ,
wherein the outer edge side of the contact electrode forms a complete loop that is laterally spaced apart from the edge surface of the semiconductor body in every direction,
wherein the passivation layer section conformally covers the outer edge side of the contact electrode around the complete loop,
wherein the inner edge sides of the first, second and third layers are laterally spaced apart from the first plane around the complete loop, and
wherein the outer edge sides of the first, second and third layers are laterally spaced apart from the outer edge side of the contact electrode around the complete loop.

5. The semiconductor device of claim 1 , further comprising:
a first doped region and a second doped region in the semiconductor body,
wherein the first doped region and the second doped region form a pn junction with one another,
wherein the pn junction extends to the first surface,
wherein the contact electrode is connected to the second doped region, and
wherein the passivation layer covers the pn junction on top of the first surface.

6. The semiconductor device of claim 1 , wherein the first layer comprises at least one of: USG, PSG, BSG, and BPSG.

7. The semiconductor device of claim 1 , wherein the second layer comprises a nitride.

8. The semiconductor device of claim 1 , wherein the third layer comprises an imide.

9. The semiconductor device of claim 1 , wherein the first layer comprises at least one of: USG, PSG, BSG, and BPSG, wherein the second layer comprises a nitride, and wherein the third layer comprises an imide.

10. The semiconductor device of claim 1 , wherein the semiconductor body comprises at least one of silicon (Si), silicon carbide (SiC), gallium arsenide (GaAs), gallium nitride (GaN), gallium phosphide (GaP), indium phosphide (InP), indium gallium nitride (InGaN), indium gallium arsenide (InGaAs), cadmium telluride (CdTe), cadmium mercury telluride (CdHgTe), and cadmium magnesium telluride (CdMgTe).

11. The semiconductor device of claim 10 , wherein the semiconductor body comprises silicon carbide (SiC).

12. The semiconductor device of claim 1 ,
wherein a thickness of the first layer is at least 1.5 micrometers, and
wherein a thickness of the second layer is at least 0.6 micrometers.

13. The semiconductor device of claim 1 , further comprising:
a soft encapsulation layer on the third layer and the contact electrode; and
a housing separated from the third layer by the soft encapsulation layer.

14. The semiconductor device of claim 13 , wherein the soft encapsulation layer is selected from the group consisting of:
silicone, and
silica gel.

15. A method of forming a semiconductor device, comprising:
providing a semiconductor body comprising a first surface and an edge surface laterally terminating the first surface;
forming a contact electrode on the first surface that comprises an outer edge side that faces and is laterally spaced apart from the edge surface; and
forming a passivation layer section that conformally covers the outer edge side of the contact electrode,
wherein the passivation layer section is a multi-layer stack comprising a first layer, a second layer, and a third layer, each of the first, second and third layers being formed from different electrically insulating materials,
wherein the first layer directly contacts the contact electrode and the first surface,
wherein the second layer is formed directly on the first layer,
wherein the third layer is formed directly on the second layer,
wherein each of the first, second and third layers comprise outer edge sides facing the edge surface of the semiconductor body and inner edge sides opposite from the outer edge sides,
wherein the outer edge side of the contact electrode extends along a first plane that is transverse to the first surface and wherein the first plane is disposed laterally between the inner edge sides and the outer edge sides of each of the first, second and third layers,
wherein the inner edge side of the third layer is laterally closer to the first plane than the inner edge side of the second layer is to the first plane, and
wherein the outer edge side of the third layer is laterally closer to the first plane than the outer edge side of the second layer is to the first plane.

16. The method of claim 15 ,
wherein the edge surface of the semiconductor body extends along a second plane that is transverse to the first surface,
wherein the outer edge sides of each of the first, second and third layers are disposed laterally between the first plane and the second plane.

17. The method of claim 15 ,
wherein inner edge sides of the first and second layers are laterally aligned with one another, and
wherein the outer edge sides of the first and second layers are laterally aligned with one another.

18. The method of claim 15 ,
wherein the outer edge side of the contact electrode forms a complete loop that is laterally spaced apart from the edge surface of the semiconductor body in every direction,
wherein the passivation layer section conformally covers the outer edge side of the contact electrode around the complete loop,
wherein the inner edge sides of the first, second and third layers are laterally spaced apart from the first plane around the complete loop, and
wherein the outer edge sides of the first, second a

Assignees

• Infineon Technologies Ag

Inventors

• Konrath Jens Peter
• Hecht Christian
• Rupp Roland
• Kabakow Andre

Classifications

• H10P50/692

  characterised by their composition, e.g. multilayer masks or materials · CPC title

• H10P14/69433

  the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz · CPC title

• H10P14/69215

  the material being a silicon oxide, e.g. SiO2 · CPC title

• H10P14/6923

  the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG · CPC title

• H10P14/6922

  the material containing Si, O and at least one of H, N, C, F or other non-metal elements, e.g. SiOC, SiOC:H or SiONC · CPC title