Semiconductor device having a corrosion-resistant metallization and method for manufacturing thereof

Patent metadata

Field	Value
Publication number	US-9355958-B2
Application number	US-201314068398-A
Country	US
Kind code	B2
Filing date	Oct 31, 2013
Priority date	Oct 31, 2013
Publication date	May 31, 2016
Grant date	May 31, 2016

Abstract

A semiconductor device includes a semiconductor substrate having a first side, a second side opposite the first side, an active area, an outer rim, and an edge termination area arranged between the outer rim and the active area. A metallization structure is arranged on the first side of the semiconductor substrate and comprising at least a first metal layer comprised of a first metallic material and a second metal layer comprised of a second metallic material, wherein the first metallic material is electrochemically more stable than the second metallic material. The first metal layer extends laterally further towards the outer rim than the second metal layer.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a semiconductor substrate comprising a first side, a second side opposite the first side, an active area, an outer rim, and an edge termination area arranged between the outer rim and the active area; and
a metallization structure arranged on the first side of the semiconductor substrate and comprising at least a first metal layer comprised of a first metallic material and a second metal layer comprised of a second metallic material, wherein the first metallic material is electrochemically more stable than the second metallic material and wherein the first metal layer is in contact with the second metal layer;
wherein the first metal layer extends laterally further towards the outer rim than the second metal layer, and
wherein the second metal layer is recessed from the outer rim so that mainly the first metal layer remains in the edge termination area.

2. A semiconductor device according to claim 1 , wherein the first metal layer is arranged on the second metal layer.

3. A semiconductor device according to claim 1 , wherein the second metal layer is arranged on the first metal layer.

4. A semiconductor device according to claim 1 , wherein the second metal layer is thicker than the first metal layer.

5. A semiconductor device according to claim 1 , wherein the second metallic material is selected from the group consisting of Al, AlSi, AlSiCu, AlCu, Cu, and combinations thereof.

6. A semiconductor device according to claim 1 , wherein the first metallic material is selected from the group consisting of TiW, Ti/TiN, WN, W, Ta/TaN, WTiN, silicides such as WSi 2 , CoSi, TiSi, highly doped poly-Si and combinations thereof.

7. A semiconductor device according to claim 1 , further comprising an electrically insulating passivation which at least partially covers the first metal layer in the edge termination area and which exposes the second metal layer in the active area.

8. A semiconductor device according to claim 7 , wherein the passivation covers the first metal layer and is partially covered by the second metal layer.

9. A semiconductor device according to claim 1 , further comprising at least a first doping region and a second doping region which are spaced apart from each other, wherein the first metal layer comprises at least a first metal portion and a second metal portion which are spaced apart from each other, wherein the first metal portion of the first metal layer is in ohmic contact with the first doping region and the second metal portion of the first metal layer is in ohmic contact with the second doping region.

10. A semiconductor device according to claim 1 , further comprising an insulating layer arranged in the edge termination area between the first side of the semiconductor substrate and the first metal layer.

11. A semiconductor device according to claim 1 , further comprising an electrically insulating passivation which completely covers the first metal layer in the edge termination area and exposes the second metal layer in the active area, wherein the first metal layer forms at least one field plate in the edge termination area, and wherein the second metal layer forms a pad for an external electrical connection.

12. A semiconductor device according to claim 1 , further comprising at least one metal ring arranged on the first side of the semiconductor substrate in the edge termination area, wherein the metal ring laterally surrounds the active area when seen onto the first side of the semiconductor substrate, and wherein the metal ring is formed by the first metal layer.

13. A semiconductor device, comprising:
a semiconductor substrate comprising a first side, a second side opposite the first side, an active area, an outer rim, and an edge termination area arranged between the outer rim and the active area;
at least a first metal structure on the first side of the semiconductor substrate at least in the edge termination area;
at least a second metal structure on the first side of the semiconductor substrate only in the active area; and
an electrically insulating passivation which covers the first metal structure in the edge termination area and exposes the second metal structure in the active area;
wherein the first metal structure is comprised of metallic material which is electrochemically more stable than a metallic material of the second metal structure.

14. A semiconductor device according to claim 13 , further comprising first doping region arranged in the active area and in ohmic contact with the second metal structure, wherein the first metal structure is in ohmic contact with a second doping region, and wherein the first metal structure extends laterally further towards the outer rim than the first doping region and the second metal structure.

15. A method for manufacturing a semiconductor device, the method comprising:
providing a semiconductor substrate comprising a first side, a second side opposite the first side, an active area, an outer rim, and an edge termination area arranged between the outer rim and the active area;
forming a first metal layer comprised of a first metallic material on the first side of the semiconductor substrate at least in the edge termination area;
forming a second metal layer comprised of a second metallic material on the first side of the semiconductor substrate in the active area, wherein the first metallic material is electrochemically more stable than the second metallic material; and
structuring the first metal layer and the second metal layer so that the first metal layer extends in the edge termination area laterally further towards the outer rim than the second metal layer, wherein the second metal layer is recessed from the outer rim so that mainly the first metal layer remains in the edge termination area.

16. A method according to claim 15 , further comprising:
forming the second metal layer on the first metal layer;
forming a first mask on the second metal layer;
etching the second metal layer and the first metal layer selectively to the first mask;
forming a second mask on the etched second metal layer; and
etching the second metal layer selectively to the second mask.

17. A method according to claim 15 , further comprising:
forming the second metal layer on the first metal layer;
forming a first mask on the second metal layer;
etching the second metal layer selectively to the first mask and the first metal layer to expose portions of the first metal layer in the edge termination area;
forming a second mask on the etched second metal layer and the exposed portions of the first metal layer; and
etching the first metal layer selectively to the second mask.

18. A method according to claim 15 , further comprising:
forming a first mask on the first metal layer;
etching the first metal layer using the first mask as etching mask;
forming the second metal layer on the etched first metal layer;
forming a second mask on the second metal layer; and
etching the second metal layer using the second mask as etching mask.

19. A method according to claim 15 , further comprising:
forming a first mask on the second metal layer;
etching the second metal layer using the first mask as etching mask to remove portions of the second metal layer arranged in the edge termination area;
forming the first metal layer on the etched second metal layer;
forming a second mask on the first metal layer; and
etching the first metal layer using the second mask as etching mask.

20. A

Assignees

• Infineon Technologies Ag

Inventors

• Schäffer Carsten
• Humbel Oliver
• Plappert Mathias
• Koprowski Angelika

Classifications

• H10W20/484

  Interconnections having extended contours, e.g. pads having mesh shape or interconnections comprising connected parallel stripes · CPC title

• H10W20/035

  combinations of barrier, adhesion or liner layers, e.g. multi-layered barrier layers · CPC title

• H10W20/4407 Primary

  Aluminium alloys · CPC title

• H10D64/112 Primary

  comprising multiple field plate segments · CPC title

• H01L2924/0002

  Electricity · mapped topic