Cache snooping mode extending coherence protection for certain requests

Patent metadata

Field	Value
Publication number	US-11157409-B2
Application number	US-201916717868-A
Country	US
Kind code	B2
Filing date	Dec 17, 2019
Priority date	Dec 17, 2019
Publication date	Oct 26, 2021
Grant date	Oct 26, 2021

Abstract

A cache memory includes a data array, a directory of contents of the data array that specifies coherence state information, and snoop logic that processes operations snooped from a system fabric by reference to the data array and the directory. The snoop logic, responsive to snooping on the system fabric a request of a first flush/clean memory access operation that specifies a target address, determines whether or not the cache memory has coherence ownership of the target address. Based on determining the cache memory has coherence ownership of the target address, the snoop logic services the request and thereafter enters a referee mode. While in the referee mode, the snoop logic protects a memory block identified by the target address against conflicting memory access requests by the plurality of processor cores until conclusion of a second flush/clean memory access operation that specifies the target address.

First claim

What is claimed is:

1. A method of data processing in a multiprocessor data processing system including a cache memory of an associated processor core among a plurality of processor cores in the multiprocessor data processing system, said multiprocessor data processing system including a system fabric communicatively coupling the cache memory and a memory controller of a system memory to receive operations on the system fabric, the method comprising:
the cache memory snooping, on the system fabric, a request of a first flush/clean memory access operation of one of the plurality of processor cores that specifies a target address;
based on snooping the request, the cache memory determining whether or not the cache memory has coherence ownership of the target address;
based on determining the cache memory has coherence ownership of the target address, the cache memory servicing the request and thereafter entering a referee mode;
while in the referee mode, the cache memory protecting a memory block identified by the target address against conflicting memory access requests by the plurality of processor cores; and
the cache memory exiting the referee mode and ending protection of the memory block identified by the target address based on a systemwide coherence response to a second flush/clean memory access operation that is snooped by the snoop logic and that specifies the target address.

2. The method of claim 1 , wherein:
the request of the flush or clean operation is a first request; and
entering the referee mode comprises entering the referee mode based on snooping a conflicting second request after snooping the first request and prior to the snoop logic completing processing of the first request.

3. The method of claim 1 , wherein the protecting comprises the cache memory protecting the memory block against conflicting memory access requests by issuing Retry coherence responses to the conflicting memory access requests.

4. The method of claim 1 , and further comprising the cache memory, while in the referee mode, providing a first coherence response for conflicting requests of a same class of flush/clean memory access operations as the first flush/clean memory access operation and providing a different second coherence response for conflicting requests of other types.

5. The method of claim 1 , and further comprising the cache memory, while in the referee mode, detecting a timeout condition, and to based on detecting the timeout condition, exiting the referee mode.

6. The method of claim 1 , wherein entering the referee mode comprises the cache memory only entering the referee mode based on the coherence state information in the directory indicating coherence ownership of a modified cache line associated with the target address.

7. A cache memory of an associated processor core among a plurality of processor cores in a multiprocessor data processing system, said multiprocessor data processing system including a system fabric communicatively coupling the cache memory and a memory controller of a system memory to receive operations on the system fabric, the cache memory comprising:
a data array;
a directory of contents of the data array, wherein the directory includes coherence state information; and
snoop logic that processes operations snooped from the system fabric by reference to the data array and the directory, wherein the snoop logic, responsive to snooping on the system fabric a request of a first flush/clean memory access operation of one of the plurality of processor cores that specifies a target address:
determines whether or not the cache memory has coherence ownership of the target address;
based on determining the cache memory has coherence ownership of the target address, services the request and thereafter enters a referee mode;
while in the referee mode, protects a memory block identified by the target address against conflicting memory access requests by the plurality of processor cores; and
exits the referee mode and ends protection of the memory block identified by the target address based on a systemwide coherence response to a second flush/clean memory access operation that is snooped by the snoop logic and that specifies the target address.

8. The cache memory of claim 7 , wherein:
the request of the flush or clean operation is a first request; and
the snoop logic is configured to enter the referee mode based on snooping a conflicting second request after snooping the first request and prior to the snoop logic completing processing of the first request.

9. The cache memory of claim 7 , wherein the snoop logic is configured to protect the memory block against conflicting memory access requests by issuing Retry coherence responses to the conflicting memory access requests.

10. The cache memory of claim 7 , wherein:
the snoop logic, while in the referee mode, is configured to provide a first coherence response for conflicting requests of a same class of flush/clean memory access operations as the first flush/clean memory access operation and to provide a different second coherence response for conflicting requests of other types.

11. The cache memory of claim 7 , wherein the snoop logic is configured, while in the referee mode, to detect a timeout condition, and in response to based on detecting the timeout condition, to exit the referee mode.

12. The cache memory of claim 7 , wherein the cache memory only enters the referee mode based on the coherence state information in the directory indicating coherence ownership of a modified cache line associated with the target address.

13. A processing unit, comprising:
memory according to claim 7 ; and
at least one affiliated processor core coupled to the cache memory.

14. A data processing system, comprising:
a system fabric; and
a plurality of processing units according to claim 13 all coupled to the system fabric.

15. A design structure tangibly embodied in a machine-readable storage device for designing, manufacturing, or testing an integrated circuit, the design structure comprising:
a processing unit, including:
a processor core;
a cache memory including:
a data array;
a directory of contents of the data array, wherein the directory includes coherence state information; and

snoop logic that processes operations snooped from the system fabric by reference to the data array and the directory, wherein the snoop logic, responsive to snooping on the system fabric a request of a first flush/clean memory access operation of one of the plurality of processor cores that specifies a target address:
determines whether or not the cache memory has coherence ownership of the target address;
based on determining the cache memory has coherence ownership of the target address, services the request and thereafter enters a referee mode;
while in the referee mode, protects a memory block identified by the target address against conflicting memory access requests by the plurality of processor cores: and
exits the referee mode and ends protection of the memory block identified by the target address based on a systemwide coherence response to a second flush/clean memory access operation that is snooped by the snoop logic and that specifies the target address.

16. The design structure of claim 15 , wherein:
the request of the flush or clean operation is a first request; and
the snoop logic is configured to enter the referee mode based on snooping a conflicting second request after snooping the first request and prior to the snoop logic completing processing of the first request.

17. The

Assignees

• IBM

Inventors

• Williams Derek E
• Guthrie Guy L
• Shen Hugh
• Murray Luke

Classifications

• G06F12/0828 Primary

  with concurrent directory accessing, i.e. handling multiple concurrent coherency transactions · CPC title

• G06F12/0855

  Overlapped cache accessing, e.g. pipeline (G06F12/0846 takes precedence) · CPC title

• G06F12/0891

  using clearing, invalidating or resetting means · CPC title

• G06F12/0833

  in combination with broadcast means (e.g. for invalidation or updating) · CPC title

• G06F12/0844

  Multiple simultaneous or quasi-simultaneous cache accessing · CPC title