Memory systems and operating methods of memory systems

Patent metadata

Field	Value
Publication number	US-11157342-B2
Application number	US-201816164103-A
Country	US
Kind code	B2
Filing date	Oct 18, 2018
Priority date	Apr 6, 2018
Publication date	Oct 26, 2021
Grant date	Oct 26, 2021

Abstract

A memory system includes a processor that includes cores and a memory controller, and a first semiconductor memory module that communicates with the memory controller. The cores receive a call to perform a first exception handling in response to detection of a first error when the memory controller reads first data from the first semiconductor memory module. A first monarchy core of the cores performs the first exception handling and the remaining cores of the cores return to remaining operations previously performed.

First claim

What is claimed is:

1. A memory system comprising:
a processor including cores and a memory controller; and
a first semiconductor memory module configured to communicate with the memory controller,
wherein the first semiconductor memory module comprises a nonvolatile memory, a random access memory, and a media controller configured to provide a storage space of the nonvolatile memory to the processor and to use the random access memory as a cache memory of the nonvolatile memory of the first semiconductor memory module,
wherein the cores receive a call to perform a first exception handling associated with a machine check exception in response to detection of a first uncorrectable error when the memory controller reads first data from the first semiconductor memory module,
wherein, responsive to determining that the first uncorrectable error is associated with an absence from the random access memory of the first data that is stored in the nonvolatile memory, a first monarchy core of the cores performs the first exception handling and remaining cores of the cores return to remaining operations previously performed, and
wherein the media controller is configured to map to the random access memory a portion of the nonvolatile memory corresponding to the first data while the first monarchy core performs the first exception handling.

2. The memory system of claim 1 , wherein the first monarchy core is a core from among the cores that first interrupts an operation being performed to perform the first exception handling in response to the call for the first exception handling.

3. The memory system of claim 2 , wherein the remaining cores return to the remaining operations previously performed responsive to determining that the first monarchy core exists.

4. The memory system of claim 1 , further comprising:
a second semiconductor memory module configured to communicate with the memory controller,
wherein, while the first monarchy core performs the first exception handling, the cores receive a second call to further perform a second exception handling responsive to detection of a second error when the memory controller reads second data from the second semiconductor memory module.

5. The memory system of claim 4 , wherein a core from the remaining cores that first interrupts an operation being performed to perform the second exception handling in response to the second call for the second exception handling is specified as a second monarchy core.

6. The memory system of claim 5 , wherein other remaining cores of the remaining cores except for the second monarchy core return to other remaining operations previously performed responsive to determining that the second monarchy core exists.

7. The memory system of claim 5 , wherein, when the first monarchy core completes the first exception handling while the second monarchy core performs the second exception handling, the first monarchy core returns to an operation previously performed.

8. The memory system of claim 1 , wherein the first uncorrectable error is broadcast to the cores responsive to the media controller accessing the nonvolatile memory when the memory controller reads the first data.

9. The memory system of claim 8 , wherein, while the first monarchy core performs the first exception handling, the media controller completes the accessing of the nonvolatile memory.

10. The memory system of claim 1 , further comprising:
a second semiconductor memory module comprising a second random access memory,
wherein, responsive to determining that a second error is generated based on access by the memory controller to the second semiconductor memory module, a second monarchy core of the cores performs a second exception handling, different from the first exception handling, responsive to the second error, and the memory system enters a kernel panic or a system reboot depending on a type of the second error.

11. A memory system comprising:
a processor comprising cores and a memory controller; and
a first semiconductor memory module configured to communicate with the memory controller and comprising a nonvolatile memory and a first random access memory configured to be used as a cache memory of the nonvolatile memory,
wherein, responsive to determining that a first error is generated based on access of first data by the memory controller to the first semiconductor memory module comprising the nonvolatile memory, a first monarchy core of the cores performs a first machine check operation responsive to the first error and returns to an operation previously performed, even though the first error indicates a system reboot or a kernel panic.

12. The memory system of claim 11 , wherein, after the first machine check operation is performed, the memory controller again reads the first data from the first semiconductor memory module.

13. The memory system of claim 11 , further comprising:
a second semiconductor memory module comprising a second random access memory,
wherein, responsive to determining that a second error is generated based on access by the memory controller to the second semiconductor memory module, a second monarchy core of the cores performs a second machine check operation, different from the first machine check operation, responsive to the second error, and the memory system enters the kernel panic or the system reboot depending on a type of the second error.

14. The memory system of claim 11 , wherein the first semiconductor memory module further comprises:
a media controller configured to control the nonvolatile memory and the first random access memory,
wherein, while the first monarchy core performs the first machine check operation, the media controller reads the first data from the nonvolatile memory and stores the first data to the first random access memory.

15. The memory system of claim 11 , wherein the first monarchy core is a core from among the cores that first responds to detection of the first error.

16. The memory system of claim 15 , wherein remaining cores of the cores other than the first monarchy core return to remaining operations previously performed responsive to determining that the first monarchy core exists.

17. The memory system of claim 11 , wherein the first error is associated with a cache miss of the first data that is stored in the nonvolatile memory.

18. An operating method of a memory system which comprises a processor comprising cores, a memory controller, a first semiconductor memory module that is a first type of memory module, and a second semiconductor memory module that is a second type of memory module, different from the first type of memory module, the method comprising:
detecting, by the memory controller, a first error upon reading data from the first semiconductor memory module, wherein the first semiconductor memory module comprises a nonvolatile memory and a random access memory, and wherein the random access memory is configured to be used as a cache memory of the nonvolatile memory of the first semiconductor memory module;
interrupting, by the cores, operations being currently performed, for exception handling of the first error;
starting, by a monarchy core of the cores, the exception handling;
returning, by remaining cores of the cores other than the monarchy core, to remaining operations of the interrupted operations, before the exception handling is completed;
responsive to determining that the first error corresponds to access of the nonvolatile memory of the first semiconductor memory module, returning, by the monarchy core, to an ope

Assignees

• Samsung Electronics Co Ltd

Inventors

• Shin Wonjae
• Ko Tae-Kyeong
• Kim Dae-Jeong
• Kim Sung-Joon
• Kim Wooseop
• Park Chanik
• Yu Yongjun
• CHOI Insu
• Byun Hui-Chung
• Lee Jongyoung

Classifications

• G06F11/0793

  Remedial or corrective actions (recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40) · CPC title

• G06F11/0727

  in a storage system, e.g. in a DASD or network based storage system (drivers for digital recording or reproducing units G06F3/06; circuits for error detection or correction within digital recording or reproducing units G11B20/18; for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS], H04L67/1097) · CPC title

• G06F11/1068

  in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence) · CPC title

• G06F12/0246

  in block erasable memory, e.g. flash memory · CPC title

• G06F11/0751 Primary

  Error or fault detection not based on redundancy (power supply failures G06F1/30; network fault management H04L41/06) · CPC title