Memristive dot product circuit based floating point computations

Patent metadata

Field	Value
Publication number	US-11157237-B2
Application number	US-201816189291-A
Country	US
Kind code	B2
Filing date	Nov 13, 2018
Priority date	Nov 13, 2018
Publication date	Oct 26, 2021
Grant date	Oct 26, 2021

Abstract

In some examples, memristive dot product circuit based floating point computations may include ascertaining a matrix and a vector including floating point values, and partitioning the matrix into a plurality of sub-matrices according to a size of a plurality of memristive dot product circuits. For each sub-matrix of the plurality of sub-matrices, the floating point values may be converted to fixed point values. Based on the conversion and selected ones of the plurality of memristive dot product circuits, a dot product operation may be performed with respect to a sub-matrix and the vector. Each ones of the plurality of memristive dot product circuits may include rows including word line voltages corresponding to the floating point values of the vector, conductances corresponding to the floating point values of an associated sub-matrix, and columns that include bitline currents corresponding to dot products of the voltages and conductances.

First claim

What is claimed is:

1. An apparatus comprising:
a processor; and
a non-transitory computer readable medium storing machine readable instructions that when executed by the processor cause the processor to:
ascertain a matrix and a vector including floating point values;
partition the matrix into a plurality of sub-matrices according to a size of a plurality of memristive dot product circuits;
for each sub-matrix of the plurality of sub-matrices, convert the floating point values to fixed point values, wherein to convert the floating point values to fixed point values further causes the processor to:
for each sub-matrix of the plurality of sub-matrices,
align mantissas of the fixed point values of a corresponding sub-matrix by independently aligning, for each row of the corresponding sub-matrix, a lowest element within the row of the corresponding sub-matrix with and a highest element within the same row of the corresponding sub-matrix; and
modify the fixed point values of the corresponding sub-matrix with the aligned mantissas to include an equal length for each row of the corresponding sub-matrix; and

perform, based on the conversion and selected ones of the plurality of memristive dot product circuits, a dot product operation with respect to a sub-matrix and the vector, wherein
each ones of the plurality of memristive dot product circuits includes rows including word line voltages corresponding to the floating point values of the vector, conductances corresponding to the floating point values of the corresponding sub-matrix, and columns that include bitline currents corresponding to dot products of the voltages and conductances.

2. The apparatus according to claim 1 , wherein the plurality of memristive dot product circuits are disposed in a plurality of clusters, and wherein the instructions are further to cause the processor to:
perform, using memristive dot product circuits of a cluster of the plurality of clusters, the dot product operation on the corresponding sub-matrix of the plurality of sub-matrices.

3. The apparatus according to claim 1 , wherein the instructions to modify the fixed point values of the corresponding sub-matrix with the aligned mantissas to include an equal length for each row of the corresponding sub-matrix further cause the processor to:
pad bits representing the mantissas with additional bits such that the fixed point values include an equal length, wherein a padding overhead for each row of the corresponding sub-matrix is limited to the difference between a minimum exponent associated with the lowest element within the row of the corresponding sub-matrix and a maximum exponent associated with the highest element within the same row of the corresponding sub-matrix.

4. The apparatus according to claim 3 , wherein the instructions to perform, based on the conversion and selected ones of the plurality of memristive dot product circuits, the dot product operation with respect to the sub-matrix and the vector are further to cause the processor to:
for each sub-matrix of the plurality of sub-matrices,
determine a number of bit cells supported by the selected ones of the plurality of memristive dot product circuits; and
map, based on the determined number of bit cells, each element of the corresponding sub-matrix to a corresponding memristive dot product circuit.

5. The apparatus according to claim 4 , wherein the instructions to perform, based on the conversion and selected ones of the plurality of memristive dot product circuits, the dot product operation with respect to the sub-matrix and the vector are further to cause the processor to:
perform, based on the mapping of each element of the corresponding sub-matrix to the memristive dot product circuit, a plurality of multiplication operations; and
for each multiplication operation of the plurality of multiplication operations, perform a shift and add operation to generate results of the plurality of multiplication operations.

6. The apparatus according to claim 5 , wherein the instructions to perform, based on the conversion and selected ones of the plurality of memristive dot product circuits, the dot product operation with respect to the sub-matrix and the vector are further to cause the processor to:
combine the results of the plurality of multiplication operations to generate a combined result; and
adjust, based on a bitslice position, a position of a significant bit of the combined result.

7. The apparatus according to claim 6 , wherein the instructions to perform, based on the conversion and selected ones of the plurality of memristive dot product circuits, the dot product operation with respect to the sub-matrix and the vector are further to cause the processor to:
adjust the combined result based on a scale associated with the corresponding sub-matrix.

8. The apparatus according to claim 4 , wherein the instructions to perform, based on the conversion and selected ones of the plurality of memristive dot product circuits, the dot product operation with respect to the sub-matrix and the vector are further to cause the processor to:
perform, based on the mapping of each element of the corresponding sub-matrix to the corresponding memristive dot product circuit, a plurality of multiplication operations; and
for each multiplication operation of the plurality of multiplication operations and for a negative floating point value of the floating point values, perform a shift and subtract operation to generate results of the plurality of multiplication operations.

9. The apparatus according to claim 1 , wherein the instructions are further to cause the processor to:
partition the vector into a plurality of sub-vectors according to the size of the plurality of memristive dot product circuits; and
for each sub-vector of the plurality of sub-vectors, convert the floating point values to fixed point values.

10. A computer implemented method comprising:
ascertaining a matrix and a vector including floating point values;
partitioning the matrix into a plurality of sub-matrices according to a size of a plurality of memristive dot product circuits that are disposed in a plurality of clusters;
for each sub-matrix of the plurality of sub-matrices, converting the floating point values to fixed point values wherein converting the floating point values to fixed point values comprises:
for each sub-matrix of the plurality of sub-matrices,
aligning mantissas of the fixed point values of a corresponding sub-matrix by independently aligning, for each row of the corresponding sub-matrix, a lowest element within the row of the corresponding sub-matrix with and a highest element within the same row of the corresponding sub-matrix; and
modifying the fixed point values of the corresponding sub-matrix with the aligned mantissas to include an equal length for each row of the corresponding sub-matrix; and

performing, based on the conversion and selected ones of the plurality of memristive dot product circuits of a cluster of the plurality of clusters, a dot product operation with respect to a sub-matrix and the vector,

each ones of the plurality of memristive dot product circuits includes rows including word line voltages corresponding to the floating point values of the vector, conductances corresponding to the floating point values of the corresponding sub-matrix, and columns that include bitline currents corresponding to dot products of the voltages and conductances.

11. The method according to claim 10 , wherein modifying the fixed point values of the corresponding sub-matrix with the aligned mantissas to include an equal length for each row of the corresponding sub-matrix comprises:
padding bits r

Assignees

• Hewlett Packard Entpr Dev Lp

Inventors

• Muralimanohar Naveen
• Feinberg Benjamin

Classifications

• G06F5/012

  in floating-point computations · CPC title

• G11C13/0002

  using resistive RAM [RRAM] elements · CPC title

• G06F7/4876 Primary

  Multiplying · CPC title

• G11C7/16

  Storage of analogue signals in digital stores using an arrangement comprising analogue/digital [A/D] converters, digital memories and digital/analogue [D/A] converters · CPC title

• H03M7/24

  Conversion to or from floating-point codes · CPC title