Communicating over portions of a communication medium

US11157200B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11157200-B2
Application numberUS-201415520242-A
CountryUS
Kind codeB2
Filing dateOct 29, 2014
Priority dateOct 29, 2014
Publication dateOct 26, 2021
Grant dateOct 26, 2021

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

An electronic card includes a support substrate, a plurality of storage devices on the support substrate, and a plurality of controllers on the support substrate to manage access of the corresponding plurality of storage devices, wherein the plurality of controllers and the plurality of storage devices are arranged to store data according to a Redundant Array of Independent Disks (RAID) mode.

First claim

Opening claim text (preview).

What is claimed is: 1. A single M.2 electronic card comprising: a single support substrate; a plurality of storage devices on the single support substrate; a plurality of physically separate controllers on the single support substrate to manage access of the corresponding plurality of storage devices, wherein the plurality of controllers and the plurality of storage devices are arranged to store data according to a Redundant Array of Independent Disks (RAID) mode, wherein each of the plurality of physically separate controllers are coupled to a single corresponding storage device of the plurality of storage devices; and a connector to a communication medium, split during a boot sequence into a plurality of distinct Peripheral Component Interconnect Express (PCIe) link portions, between the single electronic card and a port connector of a port of a host device to allow the plurality of controllers to independently communicate with the host device over a respective distinct PCIe link portion of the plurality of distinct PCIe link portions of the communication medium, wherein each of the plurality of controllers are designated to communicate over a corresponding distinct PCIe link portion of the communication medium and restricted from communicating over other physically distinct PCIe link portions of the communication medium, wherein the plurality of distinct PCIe link portions of the communication medium include: a first distinct PCIe link portion that corresponds to a first controller of the plurality of controllers on the single support substrate; and a second distinct PCIe link portion that corresponds to a second controller of the plurality of controllers on the single support substrate. 2. The single M.2 electronic card of claim 1 , wherein the second distinct PCIe link portion is exclusively utilized by the second controller and the first distinct PCIe link portion is exclusively utilized by the first controller. 3. The single M.2 electronic card of claim 1 , wherein the plurality of distinct PCIe link portions of the communication medium are physically distinct PCIe link portions, each of the physically distinct PCIe link portions having a bandwidth less than a full bandwidth of the communication medium, and wherein the plurality of controllers are to concurrently communicate over the physically distinct PCIe link portions of the communication medium. 4. The single M.2 electronic card of claim 1 , wherein the RAID mode stripes data across the plurality of storage devices. 5. The single M.2 electronic card of claim 1 , wherein the RAID mode provides redundant data. 6. The single M.2 electronic card of claim 1 , wherein the RAID mode both provides redundant data and stripes data across the plurality of storage devices. 7. The single electronic card of claim 1 , wherein the electronic card is a peripheral card directly coupled to the host device. 8. The single electronic card of claim 1 , wherein the connector includes signal pins that communicate respective signals over the communication medium to the host device. 9. The single electronic card of claim 1 , wherein the connector includes power pins to deliver a power supply voltage from the host device to the electronic card. 10. A method comprising: communicating, through a M.2 standard connector directly coupled to a port connector of a port of a host device over respective distinct portions of a communication medium, by storage controllers with the host device, the storage controllers on a single support substrate of an single M.2 card, wherein storage devices are further on the single support substrate, wherein the storage controllers communicate independently over the respective distinct portions with the host device that are designated during a boot sequence to each of the storage controllers and restricted from communicating with the host device over other distinct portions of the communication medium; wherein each of the storage controllers are coupled to a single corresponding storage device, and wherein the respective distinct portions of the communication medium include: a first distinct link portion that corresponds to a first controller of the controllers on the single support substrate; and a second distinct link portion that corresponds to a second controller of the controllers on the single support substrate; and managing, by the storage controllers, access of the corresponding storage devices according to a Redundant Array of Independent Disks (RAID) mode. 11. The method of claim 10 , wherein the communication medium includes a Peripheral Component Interconnect Express (PCIe) link. 12. The method of claim 10 , wherein the storage controllers communicate concurrently over the respective designated portions of the communication medium with the host device. 13. An article comprising at least one machine-readable storage medium storing instructions that upon execution cause a system to: split, during a boot sequence, a communication medium into a plurality of distinct portions that are used to independently communicate with a plurality of storage controllers on a single support substrate of an single M.2 Peripheral Component Interconnect Express (PCIe) card, wherein the plurality of distinct portions allow the plurality of storage controllers to independently communicate with a port connector of a port of a host device over a respective distinct portion of the plurality of portions of the communication medium that is designated to each of the plurality of controllers respectively and restricted from communicating with the host device over other distinct portions of the communication medium, wherein each of the plurality of controllers are coupled to a single corresponding storage device of the plurality of storage devices, and wherein the plurality of distinct portions of the communication medium include: a first distinct link portion that corresponds to a first controller of the plurality of controllers on the single support substrate; and a second distinct link portion that corresponds to a second controller of the plurality of controllers on the single support substrate; and access data of storage devices connected to the respective storage controllers of the single M.2 PCIe card according to a Redundant Array of Independent Disks (RAID) mode, wherein the storage devices are solid state storage devices or disk-based storage devices. 14. The article of claim 13 , wherein the splitting comprises dividing a PCIe link into a plurality of links to allow for independent communications over the respective plurality of links to the storage controllers of the single PCIe card.

Assignees

Inventors

Classifications

  • Improving or facilitating administration, e.g. storage management · CPC title

  • in relation to throughput · CPC title

  • Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

  • Non-volatile semiconductor memory arrays · CPC title

  • Improving I/O performance · CPC title

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Frequently asked questions

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What does patent US11157200B2 cover?
An electronic card includes a support substrate, a plurality of storage devices on the support substrate, and a plurality of controllers on the support substrate to manage access of the corresponding plurality of storage devices, wherein the plurality of controllers and the plurality of storage devices are arranged to store data according to a Redundant Array of Independent Disks (RAID) mode.
Who is the assignee on this patent?
Hewlett Packard Development Co
What technology area does this patent fall under?
Primary CPC classification G06F3/0658. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Oct 26 2021 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 5 related publications on this page (citations in our corpus or others sharing the same primary CPC).