Live, in-line hardware component upgrades in disaggregated systems

Patent metadata

Field	Value
Publication number	US-11153164-B2
Application number	US-201715398329-A
Country	US
Kind code	B2
Filing date	Jan 4, 2017
Priority date	Jan 4, 2017
Publication date	Oct 19, 2021
Grant date	Oct 19, 2021

Abstract

Various embodiments for performing hardware upgrades in a disaggregated computing environment. A workload is run on a disaggregated computing system while providing a new component to at least one of a plurality of component pools used by the disaggregated computing system. Point-to-point circuit wire level switching is used to switch the disaggregated system from an assigned component residing in a first of the plurality of component pools to the new component residing in a second of the plurality of component pools without interrupting the running workload.

First claim

What is claimed is:

1. A method for performing hardware upgrades in a disaggregated computing environment, by a processor device, comprising:
maintaining, in the disaggregated computing environment, a plurality of component pools each physically separated from one another and having a plurality of like-typed resources residing therein, wherein the plurality of component pools include a plurality of compute component pools, each of the plurality of compute component pools composed exclusively of processors, a plurality of memory component pools, each of the plurality of memory component pools composed exclusively of memory devices, and a plurality of storage component pools, each of the plurality of storage component pools composed exclusively of storage devices;
instantiating, in real-time, a dynamically constructed non-virtualized server entity operating as a disaggregated computing system composed of individual hardware components each selected from respective pools of the plurality of component pools, wherein the individual hardware components used to dynamically construct the disaggregated computing system are individual ones of the processors, memory devices, and storage devices respectively selected from the plurality of component pools;
running a workload on the disaggregated computing system while physically installing a new component comprised of a single processor of the processors, a single memory device of the memory devices, or a single storage device of the storage devices to at least one of the plurality of component pools used by the disaggregated computing system; and
using point-to-point circuit wire level switching to switch the disaggregated system from an assigned component residing in a first of the plurality of component pools to the new component residing in a second of the plurality of component pools without pause and interruption of the running workload; wherein the point-to-point wire level switching comprises switching an optical link established between the disaggregated computing system and the assigned component to the new component.

2. The method of claim 1 , wherein the new component is a new compute component in one of the plurality of compute component pools, the method further including:
pursuant to switching the disaggregated computing system to the new compute component in the second of the plurality of component pools, flushing an on-chip cache of the assigned component to move cached data to memory.

3. The method of claim 1 , further including continuing to run the workload while using the new component in the disaggregated computing system; and
testing the running workload to produce a test result.

4. The method of claim 3 , further including, responsive to the test result being negative, using the point-to-point circuit wire level switching to switch the disaggregated computing system back to the assigned component in the first of the plurality of component pools.

5. The method of claim 4 , wherein the new component is a new memory component in one of the plurality of memory component pools or a new storage component in one of the plurality of storage component pools, the method further including:
copying data directly from the assigned component to the new memory component or the new storage component.

6. The method of claim 5 , further including, responsive to the test result being negative, copying data directly from the new memory component or the new storage component to the assigned component before switching the disaggregated computing system back to the assigned component.

7. The method of claim 1 , wherein the new component is a new memory component in one of the plurality of memory component pools, the method further including:
establishing a link between a processing component to both the new memory component and an assigned memory component;
when new data must be read from storage, reading the new data into the new memory component in lieu of reading the new data into the assigned memory component; and
when a dirty block must be written in the assigned memory component, copying a page belonging to the dirty block to the new memory component and a data block in a cache to the copied page in the new memory component.

8. The method of claim 7 , further including, upon a number of data blocks in the cache having corresponding pages in the assigned memory component equaling zero, falling below a predetermined threshold or a predetermined time period has elapsed, copying all remaining pages from the assigned memory component to the new memory component.

9. A system for performing hardware upgrades in a disaggregated computing environment, the system comprising:
at least one processor; and
at least one non-transitory memory storing executable program code and coupled to the at least one processor, wherein, when executing the executable program code, the at least one processor:
maintains, in the disaggregated computing environment, a plurality of component pools each physically separated from one another and having a plurality of like-typed resources residing therein, wherein the plurality of component pools include a plurality of compute component pools, each of the plurality of compute component pools composed exclusively of processors, a plurality of memory component pools, each of the plurality of memory component pools composed exclusively of memory devices, and a plurality of storage component pools, each of the plurality of storage component pools composed exclusively of storage devices;
instantiates, in real-time, a dynamically constructed non-virtualized server entity operating as a disaggregated computing system composed of individual hardware components each selected from respective pools of the plurality of component pools, wherein the individual hardware components used to dynamically construct the disaggregated computing system are individual ones of the processors, memory devices, and storage devices respectively selected from the plurality of component pools;
runs a workload on the disaggregated computing system while physically installing a new component comprised of a single processor of the processors, a single memory device of the memory devices, or a single storage device of the storage devices to at least one of the plurality of component pools used by the disaggregated computing system; and
uses point-to-point circuit wire level switching to switch the disaggregated system from an assigned component residing in a first of the plurality of component pools to the new component residing in a second of the plurality of component pools without pause and interruption of the running workload; wherein the point-to-point wire level switching comprises switching an optical link established between the disaggregated computing system and the assigned component to the new component.

10. The system of claim 9 , wherein the new component is a new compute component in one of the plurality of compute component pools; and wherein the at least one processor:
pursuant to switching the disaggregated computing system to the new compute component in the second of the plurality of component pools, flushes an on-chip cache of the assigned component to move cached data to memory.

11. The system of claim 9 , wherein the at least one processor continues to run the workload while using the new component in the disaggregated computing system; and
tests the running workload to produce a test result.

12. The system of claim 11 , wherein the at least one processor, responsive to the test result being negative, uses the point-to-point circuit wire level switching to switch the disaggregated computing system back to the assigned c

Assignees

• IBM

Inventors

• Bivens John A
• Li Min
• Mahindru Ruchi
• Ramasamy Harigovind V
• Ruan Yaoping
• Salapura Valentina
• Schenfeld Eugen

Classifications

• H04L67/568

  Storing data temporarily at an intermediate stage, e.g. caching · CPC title

• H04L67/51

  Discovery or management thereof, e.g. service location protocol [SLP] or web services · CPC title

• H04L67/1095

  Replication or mirroring of data, e.g. scheduling or transport for data synchronisation between network nodes · CPC title

• H04L67/1031

  Controlling of the operation of servers by a load balancer, e.g. adding or removing servers that serve requests · CPC title

• H04L43/50

  Testing arrangements · CPC title