Remote memory access functionality in a cluster of data processing nodes

Patent metadata

Field	Value
Publication number	US-9262225-B2
Application number	US-201213728308-A
Country	US
Kind code	B2
Filing date	Dec 27, 2012
Priority date	Oct 30, 2009
Publication date	Feb 16, 2016
Grant date	Feb 16, 2016

Abstract

A server apparatus comprises a plurality of server on a chip nodes interconnected to each other through a node interconnect fabric. Each one of the server on a chip nodes has respective memory resources integral therewith. Each one of the server on a chip nodes has information computing resources accessible by one or more data processing systems. Each one of the server on a chip nodes is configured with memory access functionality enabling allocation of at least a portion of said memory resources thereof to one or more other ones of the server on a chip nodes and enabling allocation of at least a portion of said memory resources of one or more other ones of the server on a chip nodes thereto based on a workload thereof.

First claim

What is claimed is:

1. A server card system, comprising:
a first server on a chip node card having a node density configured to enable the first server on a chip node card to provide information computing resources to one or more data processing systems; and
a second server on a chip node card having a memory configuration configured to enable memory resources of the second server on a chip node card to be allocated to one or more nodes of the first server on a chip node card, wherein the second server on a chip node card is configured to:
cause a first portion of the memory resources to be allocated to a first one of the nodes of the first server on a chip node card as a private memory resource; and
cause a second portion of the memory resources to be allocated to a plurality of the nodes of the first server on a chip node card as a shared memory resource.

2. The server card system of claim 1 , wherein the second server on a chip node card is further configured to:
assess a workload of a particular one of the nodes of the first server on a chip node card; and
allocate an amount of the memory resources of the second server on a chip node card based on the workload.

3. The server card system of claim 1 , wherein:
the second server on a chip node card comprises a plurality of server on a chip nodes;
the memory resources of the second server on a chip node card are accessible by each one of the plurality of server on a chip nodes of the second server on a chip node card; and
each one of the plurality of nodes of the second server on a chip node card can access a portion of the memory resources of the second server on a chip node card and selectively allocate the respective portion of the memory resources to one or more of the nodes of the first server on a chip node card.

4. The server card system of claim 1 , wherein:
the nodes of the first server on a chip node card are each configured for inter-node communication via a node interconnect fabric established therebetween; and
the memory resources of the second server on a chip node card are allocated to the nodes of the first server on a chip node card via the node interconnect fabric.

5. The server card system of claim 4 , wherein the second server on a chip node card is further configured to:
assess a workload of a particular one of the nodes of the first server on a chip node card; and
allocate an amount of the memory resources of the second server on a chip node card based on the workload.

6. A server apparatus, comprising:
a plurality of server on a chip nodes interconnected to each other through a node interconnect fabric;
wherein each one of the server on a chip nodes has respective memory resources integral therewith;
wherein each one of the server on a chip nodes has information computing resources accessible by one or more data processing systems;
wherein each one of the server on a chip nodes is configured with memory access functionality that enables allocation of at least a portion of the memory resources thereof to one or more other ones of the server on a chip nodes based on a workload of the one or more other ones of the server on a chip nodes;
wherein a first portion of the memory resources is allocated to a first one of the plurality of server on a chip nodes as a private memory resource; and
wherein a second portion of the memory resources is allocated to a plurality of the plurality of server on a chip nodes as a shared memory resource.

7. The server apparatus of claim 6 , wherein at least one of the server on a chip nodes is further configured to:
assess the workload of the one or more other ones of the server on a chip nodes.

8. The server apparatus of claim 6 , wherein the respective memory resources of each one of the server on a chip nodes is part of a pool of memory resources accessible by each one of the server on a chip nodes.

9. The server apparatus of claim 6 , wherein:
a first portion of the respective memory resources of a particular one of the server on a chip nodes is the private memory resource; and
a second portion of the respective memory resources of the particular one of the server on a chip nodes is the shared memory resource.

10. The server apparatus of claim 9 , wherein at least one of the server on a chip nodes is further configured to:
assess the workload of the particular one of the server on a chip nodes of the server apparatus; and
allocate an amount of the memory resources of another one of the server on a chip nodes of the server apparatus to the particular one of the server on a chip nodes as the private memory resource thereof based on the workload of the particular one of the server on a chip nodes of the server apparatus.

11. A data processing facility, comprising:
a server rack having a mounting structure configured to individually receive a plurality of server rack chassis;
a first server rack chassis engaged with the mounting structure of the server rack, wherein the first server rack chassis includes a first plurality of server on a chip nodes having a node density configured to enable the server on a chip nodes of the first server rack chassis to provide information computing resources to one or more data processing systems; and
a second server rack chassis engaged with the mounting structure of the server rack, wherein the second server rack chassis includes a second plurality of server on a chip nodes interconnected to the first plurality of server on a chip nodes through a node interconnect fabric, and wherein each one of the second plurality of server on a chip nodes has a memory configuration configured to enable memory resources thereof to be allocated to one or more of the first plurality of server on a chip nodes;
wherein a first portion of the memory resources is configured to be allocated to a first one of the first plurality of server on a chip nodes of the first server rack chassis as a private memory resource; and
wherein a second portion of the memory resources is configured to be allocated to a plurality of the first plurality of server on a chip nodes of the first server rack chassis as a shared memory resource.

12. The data processing facility of claim 11 , wherein at least one of the second plurality of server on a chip nodes is further configured to:
assess a workload of a particular one of the first plurality of server on a chip nodes of the first server rack chassis; and
allocate an amount of the memory resources of the second server rack chassis based on the workload.

13. The data processing facility of claim 11 , wherein:
the memory resources of the second server rack chassis are accessible by each one of the second plurality of server on a chip nodes; and
each one of the second plurality of server on a chip nodes of the second server rack chassis are configured to access a portion of the memory resources and selectively allocate the portion of the memory resources to one or more of the first plurality of server on a chip nodes of the first server rack chassis.

14. The data processing facility of claim 11 , wherein the memory resources are allocated via the node interconnect fabric.

15. The data processing facility of claim 14 , wherein at least one of the second plurality of server on a chip nodes is further configured to:
assess a workload of a particular one of the first plurality of server on a chip nodes of the first server rack chassis; and
allocate an amount of the memory resources of the second server rack chassis based on the workload.

16. A server apparatus, comprising:
a central processing unit (CPU) subsyst

Assignees

• Iii Holdings 2 Llc

Inventors

• Davis Mark Bradley
• Evans Barry Ross
• Borland David James

Classifications

• H04L47/10

  Flow control; Congestion control · CPC title

• H04L45/00

  Routing or path finding of packets in data switching networks (routing or path finding in wireless networks H04W40/00) · CPC title

• H04L45/74

  Address processing for routing · CPC title

• G06F13/00 Primary

  Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units (interface circuits for specific input/output devices G06F3/00 {; multiprogram control therefor  G06F9/46}; multiprocessor systems  G06F15/16 ) · CPC title

• G06F13/40

  Bus structure {(for computer networks G06F15/163; for optical bus networks H04B10/25)} · CPC title