Semiconductor device

Patent metadata

Field	Value
Publication number	US-11152297-B2
Application number	US-202016893540-A
Country	US
Kind code	B2
Filing date	Jun 5, 2020
Priority date	Nov 28, 2019
Publication date	Oct 19, 2021
Grant date	Oct 19, 2021

Abstract

A semiconductor device including an interlayer insulating layer on a substrate; a conductive line on the interlayer insulating layer; and a contact plug penetrating the interlayer insulating layer, the contact plug being connected to the conductive line, wherein the contact plug includes an upper pattern penetrating an upper region of the interlayer insulating layer, the upper pattern protruding upwardly from a top surface of the interlayer insulating layer, the upper pattern includes a first portion penetrating the upper region of the interlayer insulating layer; and a second portion protruding upwardly from the top surface of the interlayer insulating layer, and a width of a lower region of the second portion in a direction parallel to a top surface of the substrate is greater than a width of an upper region of the second portion in the direction parallel to the top surface of the substrate.

First claim

What is claimed is:

1. A semiconductor device, comprising:
an interlayer insulating layer on a substrate;
a conductive line on the interlayer insulating layer; and
a contact plug penetrating the interlayer insulating layer, the contact plug being connected to the conductive line,
wherein:
the contact plug includes an upper pattern penetrating an upper region of the interlayer insulating layer, the upper pattern protruding upwardly from a top surface of the interlayer insulating layer,
the upper pattern includes:
a first portion penetrating the upper region of the interlayer insulating layer; and
a second portion protruding upwardly from the top surface of the interlayer insulating layer, and

a width of a lower region of the second portion in a direction parallel to a top surface of the substrate is greater than a width of an upper region of the second portion in the direction parallel to the top surface of the substrate.

2. The semiconductor device as claimed in claim 1 , wherein the second portion of the upper pattern covers a portion of the top surface of the interlayer insulating layer.

3. The semiconductor device as claimed in claim 2 , wherein a width of the second portion of the upper pattern is progressively lower from a bottom of the second portion toward a top of the second portion.

4. The semiconductor device as claimed in claim 1 , wherein a width of an upper region of the first portion of the upper pattern is less than the width of the lower region of the second portion of the upper pattern.

5. The semiconductor device as claimed in claim 1 , wherein:
the contact plug further includes:
a lower pattern penetrating a lower region of the interlayer insulating layer, the lower pattern being connected to the upper pattern; and
a barrier pattern between the lower pattern and the interlayer insulating layer, and

the upper pattern covers a topmost surface of the barrier pattern.

6. The semiconductor device as claimed in claim 5 , wherein the topmost surface of the barrier pattern is located at a lower height from the substrate than or substantially the same height as a topmost surface of the lower pattern.

7. The semiconductor device as claimed in claim 5 , wherein the topmost surface of the barrier pattern is located at a higher height from the substrate than a topmost surface of the lower pattern and is located at a lower height from the substrate than the top surface of the interlayer insulating layer.

8. The semiconductor device as claimed in claim 5 , wherein the topmost surface of the barrier pattern is located at substantially the same height from the substrate as the top surface of the interlayer insulating layer.

9. The semiconductor device as claimed in claim 5 , wherein the barrier pattern extends between at least a portion of the first portion of the upper pattern and the interlayer insulating layer.

10. The semiconductor device as claimed in claim 1 , wherein:
the conductive line includes:
a line pattern extending in one direction on the interlayer insulating layer; and
a line barrier pattern between the line pattern and the interlayer insulating layer,

a topmost surface of the upper pattern is located at a higher height from the substrate than the top surface of the interlayer insulating layer, and
the line barrier pattern extends from the top surface of the interlayer insulating layer onto the topmost surface of the upper pattern.

11. The semiconductor device as claimed in claim 1 , wherein:
the conductive line includes:
a line pattern extending in one direction on the interlayer insulating layer; and
a line barrier pattern between the line pattern and the interlayer insulating layer,

the line barrier pattern extends between the line pattern and the upper pattern, and
a maximum height from the substrate of a substrate-facing surface of a first part of the line barrier pattern that is on the upper pattern is higher than a height from the substrate of a substrate-facing surface of a second part of the line barrier pattern that is on the interlayer insulating layer.

12. A semiconductor device, comprising:
a gate structure on a substrate;
a lower contact plug at a side of the gate structure and connected to the substrate;
a lower interlayer insulating layer covering the gate structure and the lower contact plug;
an upper interlayer insulating layer on the lower interlayer insulating layer; and
a contact plug penetrating the upper interlayer insulating layer so as to be connected to the lower contact plug,
wherein the contact plug includes an upper pattern penetrating an upper region of the upper interlayer insulating layer, the upper pattern protruding upwardly from a top surface of the upper interlayer insulating layer.

13. The semiconductor device as claimed in claim 12 , wherein:
the upper pattern includes:
a first portion penetrating the upper region of the upper interlayer insulating layer; and
a second portion protruding upwardly from the top surface of the upper interlayer insulating layer, and

a width of a lower region of the second portion in a direction parallel to a top surface of the substrate is greater than a width of an upper region of the second portion in the direction parallel to the top surface of the substrate.

14. The semiconductor device as claimed in claim 13 , wherein the second portion of the upper pattern covers a portion of the top surface of the upper interlayer insulating layer.

15. The semiconductor device as claimed in claim 13 , wherein a width of an upper region of the first portion of the upper pattern is less than the width of the lower region of the second portion of the upper pattern.

16. The semiconductor device as claimed in claim 12 , wherein:
the contact plug further includes:
a lower pattern penetrating a lower region of the upper interlayer insulating layer, the lower pattern being connected to the upper pattern; and
a barrier pattern between the lower pattern and the upper interlayer insulating layer,

the barrier pattern extends between the lower pattern and the lower contact plug.

17. The semiconductor device as claimed in claim 12 , further comprising a conductive line on the upper interlayer insulating layer,
wherein:
the contact plug is connected to the conductive line,
the conductive line includes:
a line pattern extending in one direction on the upper interlayer insulating layer; and
a line barrier pattern between the line pattern and the upper interlayer insulating layer, and

the line barrier pattern extends between the upper pattern of the contact plug and the line pattern.

18. The semiconductor device as claimed in claim 17 , wherein:
a topmost surface of the upper pattern is located at a higher height from the substrate than the top surface of the upper interlayer insulating layer, and
the line barrier pattern extends from the top surface of the upper interlayer insulating layer onto the topmost surface of the upper pattern.

19. A semiconductor device, comprising:
an interlayer insulating layer on a substrate;
a conductive line on the interlayer insulating layer; and
a contact plug penetrating the interlayer insulating layer, the contact plug being connected to the conductive line,
wherein:
the contact plug includes a protrusion protruding upwardly from a top surface of the interlayer insulating layer,
the protrusion covers a portion of the top surface of the interlayer insulating layer, and
a width of a lower region of the protrusion in a direction parallel to a top surface of the

Assignees

• Samsung Electronics Co Ltd

Inventors

• Seo Donghee
• Lee Heonbok
• Kim Tae-Yeol
• Kim Daeyong
• Lee Dohyun

Classifications

• H10W20/4437

  the principal metal being a transition metal · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/4441

  the principal metal being a refractory metal · CPC title

• H10W20/4403

  based on metals, e.g. alloys, metal silicides (H10W20/4484 takes precedence) · CPC title