Method of generating self-test signals, corresponding circuit and apparatus

Patent metadata

Field	Value
Publication number	US-11150294-B2
Application number	US-201715691381-A
Country	US
Kind code	B2
Filing date	Aug 30, 2017
Priority date	Jan 3, 2017
Publication date	Oct 19, 2021
Grant date	Oct 19, 2021

Abstract

A radio-frequency receiver includes built-in-self-test (BIST) circuitry which generates a self-test signal. A local oscillator signal is divided. A self-test oscillation signal is generated, based, at least in part, on the frequency-divided local oscillation signal. The self-test signal is generated based on the self-test oscillation signal. The BIST circuitry includes a divider, which divides the self-test oscillation signal. The frequency-divided local oscillation signal and the divided self-test oscillation signal are used to perform one or more of generating the self-test oscillation signal and controlling the generation of the self-test oscillation signal. The radio-frequency receiver may be an automotive radar receiver.

First claim

The invention claimed is:

1. A method, comprising:
applying frequency division to a local oscillator signal of a radio-frequency receiver, producing a frequency-divided signal; and
generating a self-test signal of the radio-frequency receiver using a phase-locked loop (PLL) circuit having an output oscillator, an input comparator, and a loop divider, wherein the loop divider is coupled between the output oscillator and the input comparator, with an input of the loop divider coupled to an output of the output oscillator and an output of the loop divider coupled to a first input of the input comparator, the generating of the self-test signal of the radio-frequency receiver including:
generating the self-test signal based on the frequency-divided signal; and
monitoring generation of the self-test signal using the frequency-divided signal;

supplying the frequency-divided signal to a second input of the input comparator of the PLL circuit; and
selectively varying a division factor of said loop divider, varying a frequency of said self-test signal.

2. The method of claim 1 , comprising delaying the frequency-divided signal supplied to the second input of the input comparator.

3. A circuit, comprising:
a first frequency divider, which, in operation, frequency divides a first oscillation signal, generating a first frequency-divided signal; and
self-test signal generation circuitry that includes a phase-locked loop (PLL) having an output oscillator, an input comparator, and a loop divider, wherein the loop divider is coupled between the output oscillator and the input comparator, with an output of the output oscillator coupled to an input of the loop divider and an output of the loop divider coupled to a first input of the input comparator, wherein a second input of the input comparator is coupled to an output of the first frequency divider and wherein the self-test signal generation circuitry, in operation, generates a receiver self-test signal, the generating of the receiver self-test signal including:
generating the self-test signal based on the first frequency-divided signal; and
monitoring generation of the self-test signal using the first frequency-divided signal, wherein a division factor of the loop divider is adjustable and, in operation, varying the division factor of the loop divider varies a frequency of the self-test signal.

4. The circuit of claim 3 , comprising a delay circuit coupled between the output of the first frequency divider and the second input of the input comparator of the PLL.

Assignees

• St Microelectronics Srl

Inventors

• Maiellaro Giorgio
• Scuderi Angelo
• Bruno Angela
• Scaccianoce Salvatore

Classifications

• G01S7/4056 Primary

  specially adapted to FMCW · CPC title

• G01S7/4069

  involving a RF signal injection · CPC title

• G01R31/2884 Primary

  using dedicated test connectors, test elements or test circuits on the IC under test (G01R31/2855 takes precedence) · CPC title

• H04B17/0085 Primary

  using test signal generators · CPC title

• H03C3/0916

  with frequency divider or counter in the loop · CPC title