Interlocking modular beamformer

US11145977B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11145977-B2
Application numberUS-201916441837-A
CountryUS
Kind codeB2
Filing dateJun 14, 2019
Priority dateJun 14, 2019
Publication dateOct 12, 2021
Grant dateOct 12, 2021

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

An array includes a support structure configured to support columns of beamformer assemblies, and a plurality of beamformer assemblies supported by the support structure. Each beamformer assembly includes at least one beamformer having at least one first beamformer segment and at least one second beamformer segment configured to interconnect with the first beamformer segment.

First claim

Opening claim text (preview).

What is claimed is: 1. An array comprising: a support structure configured to support columns of beamformer assemblies; and a plurality of beamformer assemblies supported by the support structure, each beamformer assembly including at least one beamformer having at least one first beamformer segment and at least one second beamformer segment configured to interconnect with the first beamformer segment, wherein each beamformer segment of the first beamformer segment and the second beamformer segment is secured to one another by an RF connector or by a SNAP-RF edge interface, and wherein, for each beamformer segment of the first beamformer segment and the second beamformer segment, the edge interface is provided along each side edge of the segment to enable adjacently placed segments to be snap-fit connected to one another. 2. The array of claim 1 , wherein the plurality of beamformer assemblies include a randomized assortment of beamformers with varying numbers of inputs from 3 to 8. 3. The array of claim 1 , wherein the first beamformer segment functions as a TX line and the second beamformer segment functions as a combiner. 4. The array of claim 1 , wherein each beamformer further includes terminal segments provided at ends of the beamformer. 5. The array of claim 1 , wherein the at least one beamformer further includes between two and eight ports. 6. The array of claim 5 , wherein each first beamformer segment includes a first input provided on a side of the segment and a second input provided on an opposite side of the segment. 7. The array of claim 6 , wherein each second beamformer segment includes a first input provided on a side of the segment and a second input provided on an opposite side of the segment. 8. The array of claim 7 , wherein each second beamformer segment further includes an output provided on one side of the segment. 9. The array of claim 1 , wherein the at least one beamformer further includes at least one of a vertical launch and a Faraday wall. 10. A beamformer comprising: at least one first beamformer segment; and at least one second beamformer segment configured to interconnect with the first beamformer segment, wherein each beamformer segment of the first beamformer segment and the second beamformer segment is secured to one another by an RF connector or a SNAP-RF edge interface, and wherein, for each beamformer segment of the first beamformer segment and the second beamformer segment, the edge interface is provided along each side edge of the segment to enable adjacently placed segments to be snap-fit connected to one another. 11. The beamformer of claim 10 , wherein the beamformer includes one of a 3:1 beamformer, a 5:1 beamformer, and a 8:1 beamformer. 12. The beamformer of claim 10 , wherein the first beamformer segment functions as a TX line and the second beamformer segment functions as a combiner. 13. The beamformer of claim 12 , wherein a number of inputs of the beamformer can be expanded between 2 and 8 inputs by attaching additional TX line boards. 14. The beamformer of claim 10 , further comprising terminal segments provided at ends of the beamformer. 15. The beamformer of claim 10 , wherein each first beamformer segment includes a first input provided on a side of the segment and a second input provided on an opposite side of the segment, each second beamformer segment includes a first input provided on a side of the segment and a second input provided on an opposite side of the segment, and each second beamformer segment further includes an output provided on one side of the segment. 16. The beamformer of claim 10 , wherein each second beamformer segment further includes an output provided on one side of the segment, each second beamformer segment being configured to provide signal crossover to connect adjacent segments to support dual polarization.

Assignees

Inventors

Classifications

  • Adding a circuit layer by thick film methods, e.g. printing techniques or by other techniques for making conductive patterns by using pastes, inks or powders (H05K3/4647 takes precedence) · CPC title

  • by ink-jet printing or drawing by dispensing · CPC title

  • Structural association of two or more printed circuits (providing electric connection to or between printed circuits H05K1/11, H01R12/00) · CPC title

  • Printed circuits associated with mounted high frequency components · CPC title

  • Antennas or antenna systems providing at least two radiating patterns (arrangements for changing or varying the orientation or the shape of the directional pattern H01Q3/00) · CPC title

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Frequently asked questions

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What does patent US11145977B2 cover?
An array includes a support structure configured to support columns of beamformer assemblies, and a plurality of beamformer assemblies supported by the support structure. Each beamformer assembly includes at least one beamformer having at least one first beamformer segment and at least one second beamformer segment configured to interconnect with the first beamformer segment.
Who is the assignee on this patent?
Raytheon Co
What technology area does this patent fall under?
Primary CPC classification H01Q3/30. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Oct 12 2021 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).