Process for forming metal-insulator-metal structures

Patent metadata

Field	Value
Publication number	US-11145592-B2
Application number	US-202016787933-A
Country	US
Kind code	B2
Filing date	Feb 11, 2020
Priority date	Feb 11, 2020
Publication date	Oct 12, 2021
Grant date	Oct 12, 2021

Abstract

Semiconductor devices and methods of forming the same are provided. A method according to an embodiment includes receiving a substrate including a lower contact feature, depositing a first dielectric layer over a substrate, forming a metal-insulator-metal (MIM) structure over the first dielectric layer, depositing a second dielectric layer over the MIM structure, performing a first etch process to form an opening that extends through the second dielectric layer to expose the MIM structure, performing a second etch process to extend the opening through the MIM structure to expose the first dielectric layer; and performing a third etch process to further extend the opening through the first dielectric layer to expose the lower contact feature. Etchants of the first etch process and the third etch process include fluorine while the etchant of the second etch process is free of fluorine.

First claim

What is claimed is:

1. A method, comprising:
receiving a substrate including a lower contact feature;
depositing a first dielectric layer over a substrate;
forming a metal-insulator-metal (MIM) structure over the first dielectric layer;
depositing a second dielectric layer over the MIM structure;
performing a first etch process to form an opening that extends through the second dielectric layer to expose the MIM structure;
performing a second etch process to extend the opening through the MIM structure to expose the first dielectric layer; and
performing a third etch process to further extend the opening through the first dielectric layer to expose the lower contact feature,
wherein the first etch process comprises a first etchant, the second etch process comprises a second etchant, and the third etch process comprises a third etchant,
wherein the first etchant and the third etchant comprise fluorine,
wherein the second etchant does not include fluorine.

2. The method of claim 1 , wherein the MIM structure comprises a conductor plate layer formed of titanium nitride, tantalum nitride, titanium, or tantalum.

3. The method of claim 1 , wherein the MIM structure comprises an insulator layer formed of zirconium oxide, hafnium oxide, aluminum oxide, tantalum oxide, silicon oxide, or titanium oxide.

4. The method of claim 1 , wherein the first etchant comprises sulfur hexafluoride.

5. The method of claim 1 , wherein the second etchant comprises chlorine.

6. The method of claim 1 , wherein the third etchant comprises carbon tetrafluoride.

7. The method of claim 1 , wherein the lower contact feature comprises copper.

8. A method, comprising:
receiving a substrate including a lower contact feature;
depositing a silicon nitride layer over a substrate, including over the lower contact feature;
depositing a first silicon oxide layer over the silicon nitride layer;
forming a conductor plate layer over the first silicon oxide layer;
depositing a second silicon oxide layer over the conductor plate layer;
performing a first etch process to form an opening through the second silicon oxide layer to expose the conductor plate layer;
performing a second etch process to extend the opening through the conductor plate layer to expose the first silicon oxide layer; and
performing a third etch process to further extend the opening through the first silicon oxide layer and the silicon nitride layer to expose the lower contact feature,
wherein the first etch process comprises a first etchant, the second etch process comprises a second etchant, and the third etch process comprises a third etchant,
wherein the first etchant and the third etchant comprise fluorine,
wherein the second etchant consists essentially of chlorine.

9. The method of claim 8 , wherein the conductor plate layer comprises titanium nitride, tantalum nitride, titanium, or tantalum.

10. The method of claim 8 , further comprising depositing an insulator layer over the conductor plate layer, wherein the insulator layer is formed of zirconium oxide, hafnium oxide, aluminum oxide, tantalum oxide, silicon oxide, or titanium oxide.

11. The method of claim 8 ,
wherein the first etchant comprises sulfur hexafluoride,
wherein the third etchant comprises carbon tetrafluoride.

12. The method of claim 8 , wherein the second etchant is selected such that no reaction between the second etchant and the conductor plate layer produces a non-volatile byproduct.

13. The method of claim 8 , wherein the opening penetrates the conductor plate layer with a linear taper.

14. The method of claim 8 , further comprising:
forming a contact via through the opening to be in contact with the lower contact feature.

15. The method of claim 14 ,
wherein the contact via comprises a barrier layer and a metal fill layer,
wherein the barrier layer and the conductor plate layer comprise the same composition,
wherein the metal fill layer comprises copper and aluminum.

16. A semiconductor device, comprising:
a lower contact feature;
a first dielectric layer over the lower contact feature;
a metal-insulator-metal (MIM) structure over the first dielectric layer;
a second dielectric layer over the MIM structure; and
a contact via extending through the first dielectric layer, the MIM structure, and the second dielectric layer to be in direct contact with the lower contact feature, the contact via comprising a first portion through a thickness of the first dielectric layer, a second portion through a thickness of the MIM structure, and a third portion through a thickness of the second dielectric layer,
wherein the first portion tapers substantially linearly at a first angle,
wherein the second portion tapers substantially linearly at a second angle greater than the first angle,
wherein the third portion tapers substantially linearly at a third angle smaller than the second angle.

17. The semiconductor device of claim 16 ,
wherein the MIM structure comprises a conductor plate layer,
wherein the contact via comprises a barrier layer and a metal fill layer embedded in the barrier layer,
wherein the barrier layer and the conductor plate comprise titanium, tantalum, titanium nitride, or tantalum nitride,
wherein the metal fill layer comprises copper and aluminum.

18. The semiconductor device of claim 16 , wherein the MIM structure comprises an insulator layer formed of zirconium oxide, hafnium oxide, aluminum oxide, tantalum oxide, silicon oxide, or titanium oxide.

19. The semiconductor device of claim 16 , wherein an interface between the contact via and the MIM structure is free of metal fluoride.

20. The semiconductor device of claim 16 ,
wherein the first angle is between about 0° and about 10°,
wherein the second angle is between about 35° and about 45°
wherein the third angle is between about 15° and about 20°.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Shen Hsiang-Ku
• Huang Jian-Ming
• Chen Han-Yi
• Lu Ecko
• Tsai Hsiang-Yu
• Lu Chih-Hung
• Chen Wen-Tung

Classifications

• H10P14/69395

  the material containing zirconium, e.g. ZrO2 · CPC title

• H10P14/69394

  the material containing titanium, e.g. TiO2 · CPC title

• H10P14/69393

  the material containing tantalum, e.g. Ta2O5 · CPC title

• H10P14/69392

  the material containing hafnium, e.g. HfO2 · CPC title

• H10P14/69391

  the material containing aluminium, e.g. Al2O3 · CPC title