Display panel and method for manufacturing same

Patent metadata

Field	Value
Publication number	US-11145561-B2
Application number	US-201916644511-A
Country	US
Kind code	B2
Filing date	Apr 18, 2019
Priority date	Dec 18, 2018
Publication date	Oct 12, 2021
Grant date	Oct 12, 2021

Abstract

The present disclosure provides a display panel and a method for manufacturing the same. The method includes providing a substrate including a display area and a non-display area. A chip on film (COF) and a testing structure are disposed in the non-display area. A testing circuit includes a signal trace including a non-metal trace and a metal trace connecting to each other. A cutting line is disposed on the signal trace. The method further includes testing the display area of the substrate by the testing structure, and removing a test pad.

First claim

What is claimed is:

1. A method for manufacturing a display panel, comprising:
a step S 10 of providing a substrate, wherein the substrate comprises a display area and a non-display area surrounding the display area, and a chip on film (COF) and a testing structure are disposed in the non-display area;
wherein the testing structure comprises:
a test pad disposed at a side of the COF remote from the display area; and
a testing circuit positioned between the test pad and the COF and including a signal trace connecting the COF and the test pad, wherein the signal trace comprises a non-metal trace and a metal trace connected to each other, and a cutting line is disposed on the signal trace;
a step S 20 of testing the display area of the substrate by the testing structure; and
a step S 30 of removing the test pad along the cutting line, so as to form the display panel.

2. The method for manufacturing the display panel according to claim 1 , wherein in the step S 10 , the signal trace comprises the metal trace at two ends of the signal trace and the non-metal trace in middle of the signal trace, the metal trace comprises a first metal trace connected to the COF and a second metal trace connected to the test pad, the cutting line is disposed in a region where the non-metal trace is disposed.

3. The method for manufacturing the display panel according to claim 2 , wherein the cutting line intersects the non-metal trace, and a distance between the cutting line and either one of two ends of the non-metal trace is greater than or equal to 100 μm.

4. The method for manufacturing the display panel according to claim 2 , wherein the cutting line intersects the second metal trace, and the non-metal trace has a length of 100-150 μm.

5. The method for manufacturing the display panel according to claim 2 , wherein
each of m adjacent COFs constitute a COF unit, the test pads are disposed to correspond to the COF units one by one, m is an integer greater than or equal to one;
the testing circuit comprises a plurality of transistors having a same number as number of the COFs, the transistors are disposed to correspond to the COFs one by one, the transistors are electrically connected to the second metal trace;
the transistors having a same sequence number by counting the COF units from left to right and where the COFs correspond are electrically connected to each other to constitute a transistor unit, and the testing circuit controls testing of the display area by turning on and turning off the transistor unit.

6. The method for manufacturing the display panel according to claim 1 , wherein
the substrate comprises a baseplate, a polysilicon layer, a buffer layer, and a metal layer disposed in a stacking relationship;
the non-metal trace is disposed in the polysilicon layer, the metal trace is disposed in the metal layer, the buffer layer includes a through-hole, and the non-metal trace is electrically connected to the metal trace via the through-hole to constitute the signal trace.

7. The method for manufacturing the display panel according to claim 6 , wherein the substrate further comprises a planarization layer, the planarization layer includes a recess, the COF and the test pad are disposed in the recess.

8. The method for manufacturing the display panel according to claim 1 , wherein the non-metal trace is made of polysilicon, and the metal trace is one of a gate wiring, a source and drain wiring, and a transparent metal wiring.

9. The method for manufacturing the display panel according to claim 1 , wherein the step S 30 comprises using a laser cutting technique to remove the test pad along the cutting line, so as to form the display panel.

10. A display panel comprising a display area and a non-display area surrounding the display area;
wherein the display area comprises:
a baseplate;
a polysilicon layer disposed on the baseplate and comprising a non-metal trace;
a buffer layer disposed on the polysilicon layer and including a through-hole;
a planarization layer disposed on the buffer layer and including a recess; and
a metal layer disposed on the buffer layer and comprising a metal trace, wherein the metal trace is electrically connected to the non-metal trace via the through-hole, and the metal trace is disposed in the recess;
wherein the non-display area comprises a chip on film (COF) and the non-metal trace configured to prevent the metal trace from erosion, and the COF is electrically connected to one of the non-metal trace and the metal trace.

11. A method for manufacturing a display panel, comprising:
a step S 10 of providing a substrate, wherein the substrate comprises a display area and a non-display area surrounding the display area, and a chip on film (COF) and a testing structure are disposed in the non-display area;
wherein the testing structure comprises:
a test pad disposed at a side of the COF remote from the display area, wherein the test pads are disposed to correspond to the COFs one by one; and
a testing circuit positioned between the test pad and the COF and including a signal trace connecting the COF and the test pad, wherein the signal trace comprises a non-metal trace and a metal trace connected to each other, and a cutting line is disposed on the signal trace;
a step S 20 of testing the display area of the substrate by the testing structure; and
a step S 30 of removing the test pad along the cutting line, so as to form the display panel.

12. The method for manufacturing the display panel according to claim 11 , wherein in the step S 10 , the signal trace comprises the metal trace at two ends of the signal trace and the non-metal trace in middle of the signal trace, the metal trace comprises a first metal trace connected to the COF and a second metal trace connected to the test pad, the cutting line is disposed in a region where the non-metal trace is disposed.

13. The method for manufacturing the display panel according to claim 12 , wherein the cutting line intersects the non-metal trace, and a distance between the cutting line and either one of two ends of the non-metal trace is greater than or equal to 100 μm.

14. The method for manufacturing the display panel according to claim 12 , wherein the cutting line intersects the second metal trace, and the non-metal trace has a length of 100-150 μm.

15. The method for manufacturing the display panel according to claim 12 , wherein
each of m adjacent COFs constitute a COF unit, the test pads are disposed to correspond to the COF units one by one, m is an integer greater than or equal to one;
the testing circuit comprises a plurality of transistors having a same number as number of the COFs, the transistors are disposed to correspond to the COFs one by one, the transistors are electrically connected to the second metal trace;
the transistors having a same sequence number by counting the COF units from left to right and where the COFs correspond are electrically connected to each other to constitute a transistor unit, and the testing circuit controls testing of the display area by turning on and turning off the transistor unit.

16. The method for manufacturing the display panel according to claim 11 , wherein
the substrate comprises a baseplate, a polysilicon layer, a buffer layer, and a metal layer disposed in a stacking relationship;
the non-metal trace is disposed in the polysilicon layer, the metal trace is disposed in the metal layer, the buffer layer includes a through-hole, and the non-metal trace is electrically connected to the metal trace via the through-hole to constitute the signal trace.

Assignees

• Wuhan China Star Optoelectronics Semiconductor Display Tech Co Ltd

Inventors

• Ming Xing
• Chen Caiqin
• Wang Yiyi

Classifications

• H10P74/203

  Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects · CPC title

• H10P74/277 Primary

  Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers · CPC title

• H10P74/207

  Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics · CPC title

• H10P74/23

  characterised by multiple measurements, corrections, marking or sorting processes · CPC title

• H10P74/273 Primary

  Interconnections for measuring or testing, e.g. probe pads · CPC title