High resistivity silicon-on-insulator structure and method of manufacture thereof

Patent metadata

Field	Value
Publication number	US-11145538-B2
Application number	US-201916582447-A
Country	US
Kind code	B2
Filing date	Sep 25, 2019
Priority date	Dec 5, 2016
Publication date	Oct 12, 2021
Grant date	Oct 12, 2021

Abstract

A multilayer structure is provided, the multilayer structure comprising a semiconductor on insulator structure comprises an insulating layer that enhances the stability of the underlying charge trapping layer.

First claim

What is claimed is:

1. A method of preparing a multilayer structure, the method comprising:
depositing a charge trapping layer on a front surface of a single crystal semiconductor handle substrate, wherein the single crystal semiconductor handle substrate comprises two major, generally parallel surfaces, one of which is the front surface of the single crystal semiconductor handle substrate and the other of which is a back surface of the single crystal semiconductor handle substrate, an imaginary central plane between the front surface and the back surface, a circumferential edge joining the front and back surfaces of the single crystal semiconductor handle substrate, and a bulk region between the front and back surfaces of the single crystal semiconductor handle substrate, wherein the single crystal semiconductor handle substrate has a minimum bulk region resistivity of at least about 500 ohm-cm and further wherein the charge trapping layer comprises polycrystalline silicon and has a minimum resistivity of at least about 1000 ohm-cm;
depositing an insulating layer comprising silicon nitride or silicon oxynitride on the charge trapping layer comprising the polycrystalline silicon layer; and
bonding a dielectric layer in interfacial contact with a front surface of a single crystal semiconductor donor substrate to the insulating layer to thereby form a bonded structure, wherein the single crystal semiconductor donor substrate comprises two major, generally parallel surfaces, one of which is the front surface of the semiconductor donor substrate and the other of which is a back surface of the semiconductor donor substrate, a circumferential edge joining the front and back surfaces of the semiconductor donor substrate, a central plane between the front and back surfaces of the semiconductor donor substrate, and a bulk region between the front and back surfaces of the semiconductor donor substrate, and further wherein the single crystal semiconductor donor substrate comprises a cleave plane.

2. The method of claim 1 wherein the single crystal semiconductor handle substrate comprises single crystal silicon.

3. The method of claim 1 wherein the single crystal semiconductor handle substrate comprises a single crystal silicon wafer sliced from a single crystal silicon ingot grown by the Czochralski method or the float zone method.

4. The method of claim 1 wherein the single crystal semiconductor donor substrate comprises single crystal silicon.

5. The method of claim 1 wherein the single crystal semiconductor donor substrate comprises a single crystal silicon wafer sliced from a single crystal silicon ingot grown by the Czochralski method or the float zone method.

6. The method of claim 1 wherein the single crystal semiconductor handle substrate has a bulk resistivity between about 500 Ohm-cm and about 100,000 Ohm-cm.

7. The method of claim 1 wherein the single crystal semiconductor handle substrate has a bulk resistivity between about 1000 Ohm-cm and about 100,000 Ohm-cm.

8. The method of claim 1 wherein the single crystal semiconductor handle substrate has a bulk resistivity between about 1000 Ohm-cm and about 6,000 Ohm-cm.

9. The method of claim 1 wherein the single crystal semiconductor handle substrate has a bulk resistivity between about 3000 Ohm-cm and about 5,000 Ohm-cm.

10. The method of claim 1 wherein the charge trapping layer has a minimum resistivity of at least about 3000 ohm-cm.

11. The method of claim 1 wherein the charge trapping layer has a minimum resistivity of at least about 7000 ohm-cm.

12. The method of claim 1 wherein the insulating layer comprises silicon nitride.

13. The method of claim 12 wherein the silicon nitride is deposited by plasma enhanced chemical vapor deposition.

14. The method of claim 1 wherein the insulating layer comprises silicon oxynitride.

15. The method of claim 14 wherein the silicon oxynitride is deposited by plasma enhanced chemical vapor deposition.

16. The method of claim 1 wherein the insulating layer has a thickness between about 2000 angstroms and about 10,000 angstroms.

17. The method of claim 1 wherein the dielectric layer comprises a material selected from the group consisting of silicon dioxide, silicon nitride, silicon oxynitride, hafnium oxide, titanium oxide, zirconium oxide, lanthanum oxide, barium oxide, and a combination thereof.

18. The method of claim 1 wherein the dielectric layer comprises a material selected from the group consisting of silicon dioxide, silicon nitride, silicon oxynitride, and a combination thereof.

19. The method of claim 1 wherein the dielectric layer silicon dioxide.

20. The method of claim 1 wherein the dielectric layer comprises a multilayer, each insulating layer within the multilayer comprising a material selected from the group consisting of silicon dioxide, silicon oxynitride, and silicon nitride.

21. The method of claim 1 wherein the dielectric layer comprises an insulating layer having a thickness of at least about 10 nanometer thick, such as between about 10 nanometers and about 10,000 nanometers, between about 10 nanometers and about 5,000 nanometers, between 50 nanometers and about 400 nanometers, or between about 100 nanometers and about 400 nanometers, such as about 50 nanometers, 100 nanometers, or 200 nanometers.

22. The method of claim 1 further comprising plasma activating the insulating layer prior to bonding to the dielectric layer on the front surface of the single crystal semiconductor donor substrate.

23. The method of claim 1 further comprising annealing the bonded structure at a temperature and duration sufficient to strengthen the bond between the dielectric layer on the front surface of the single crystal semiconductor donor substrate to the insulating layer.

24. The method of claim 1 further comprising cleaving the bonded structure along the cleave plane to thereby prepare a cleaved structure comprising the single crystal semiconductor handle substrate, the charge trapping layer, the insulating layer, and a single crystal semiconductor device layer.

Assignees

• Globalwafers Co Ltd

Inventors

• Libbert Jeffery L
• Liu Qingmin
• Wang Gang
• Jones Andrew M

Classifications

• H10P90/1916

  with separation or delamination along an ion implanted layer, e.g. Smart-cut · CPC title

• H10P14/69433 Primary

  the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz · CPC title

• H10P14/69215

  the material being a silicon oxide, e.g. SiO2 · CPC title

• H10P14/6927 Primary

  the material being a silicon oxynitride, e.g. SiON or SiON:H · CPC title

• H10P14/6682

  the compound being a silane, e.g. disilane, methylsilane or chlorosilane · CPC title