Method making it possible to obtain on a crystalline substrate a semi-polar layer of nitride obtained with at least one of the following materials: gallium (Ga), indium (In) and aluminium (Al)

Patent metadata

Field	Value
Publication number	US-11139167-B2
Application number	US-201615736270-A
Country	US
Kind code	B2
Filing date	Jun 16, 2016
Priority date	Jun 18, 2015
Publication date	Oct 5, 2021
Grant date	Oct 5, 2021

Abstract

A method making it possible to obtain, on an upper surface of a crystalline substrate, a semipolar layer of nitride material comprising any one from among gallium, aluminium or indium, the method comprises the following steps: obtaining, on the upper surface of the crystalline substrate, a plurality of parallel grooves which extend in a first direction, one of the two opposite facets exhibiting a crystal orientation; etching a plurality of parallel slices which extend in a second direction that has undergone a rotation with respect to the first direction of the grooves in such a way as to obtain individual facets exhibiting a crystal orientation; epitaxial growth of the material from the individual facets.

First claim

The invention claimed is:

1. A microelectronic device comprising a crystalline substrate and a semipolar layer of at least one material comprising nitride (N) and at least one of gallium (Ga), indium (In) and aluminum (Al) on an upper surface of said crystalline substrate,
the substrate comprising a plurality of parallel grooves that extend in a first direction, each groove comprising at least two opposite inclined facets each forming a continuous band that extends in said first direction, at least one of said two opposite facets having a crystal orientation {111};
wherein the substrate also comprises a plurality of parallel trenches that extend in a second direction, said second direction being non-parallel to said first direction;
the combination of the plurality of the parallel grooves and the plurality of the parallel trenches defines an array of individual facets having the crystal orientation {111};
wherein said array comprises at least three parallel trenches and at least three parallel grooves,
the trenches and the grooves each having a bottom, the bottom all of the trenches comprised by the substrate being located below the bottom all of the grooves comprised by the substrate;
said material being in direct contact with the individual facets having the crystal orientation;
the device also comprising a masking layer arranged between the substrate and said material and that covers the whole of the upper surface of the substrate apart from the individual facets having the crystal orientation,
wherein said material is not in direct contact with the bottom of the trenches.

2. The microelectronic device as claimed in claim 1 , wherein the plurality of parallel grooves have a pitch p1, in which the plurality of parallel trenches have a pitch p2 that is between 0.8*p1 and 1.2*p1 and wherein the small angle defined by said first and second directions is greater than 40°, and is preferably greater than 60°.

3. Light-emitting diodes comprising a microelectronic device as claimed in claim 1 .

Assignees

• Commissariat Energie Atomique
• Centre Nat Rech Scient

Inventors

• El Khoury Maroun Michel
• Feuillet Guy
• Vennegues Philippe
• Zuniga Perez Jesus

Classifications

• H10P50/644

  Anisotropic liquid etching (H10P50/61 takes precedence) · CPC title

• H10P14/3416

  Nitrides · CPC title

• H10P14/3216

  Nitrides · CPC title

• H10P14/2926

  Crystal orientations · CPC title

• H10P14/2925

  Surface structures · CPC title