Gate electrode and method for manufacturing the same, and method for manufacturing array substrate

Patent metadata

Field	Value
Publication number	US-11133196-B2
Application number	US-201816303959-A
Country	US
Kind code	B2
Filing date	May 23, 2018
Priority date	May 26, 2017
Publication date	Sep 28, 2021
Grant date	Sep 28, 2021

Abstract

A gate electrode and a method for manufacturing the same, and a method for manufacturing an array substrate are provided. The method for manufacturing a gate electrode may include: providing a substrate, wherein the substrate includes a gate electrode region and a non-gate electrode region; and forming a gate electrode layer on the substrate, wherein the gate electrode layer includes a conductive portion corresponding to the gate electrode region and a transparent portion corresponding to the non-gate electrode region. According to the gate electrode and the method for manufacturing the same, and the method for manufacturing an array substrate, step difference can be eliminated, thereby avoiding an influence of the step difference on the crystallization property of a polysilicon material when an Excimer Laser Annealing (ELA) process is performed on the amorphous silicon layer, and obtaining a better crystallization effect.

First claim

What is claimed is:

1. A method for manufacturing a gate electrode, comprising:
a step S 1 of providing a substrate, the substrate comprising a gate electrode region and a non-gate electrode region; and
a step S 2 of forming a gate electrode layer on the substrate, the gate electrode layer comprising a conductive portion corresponding to the gate electrode region and a transparent portion corresponding to the non-gate electrode region,
wherein the conductive portion has a thickness equal to a thickness of the transparent portion.

2. The method according to claim 1 , wherein the step S 2 further comprises:
a step S 21 of forming a metal material layer on the substrate;
a step S 22 of forming a patterned mask layer on the metal material layer, so that a portion of the metal material layer corresponding to the gate electrode region is covered by the patterned mask layer; and
a step S 23 of oxidizing a portion of the metal material layer corresponding to the non-gate electrode region to a transparent oxide layer by oxidizing the portion of the metal material layer corresponding to the non-gate electrode region.

3. The method according to claim 2 , wherein
the metal material layer is a metal layer of tantalum, and
the transparent oxide layer is a transparent layer of tantalum oxide.

4. The method according to claim 3 , wherein the transparent layer of tantalum oxide contains tantalum trioxide or tantalum pentoxide.

5. The method according to claim 2 , wherein the step S 22 further comprises:
a step S 221 of forming a mask layer on an entire surface of the metal material layer; and
a step S 222 of patterning the mask layer by performing a photolithography process on the mask layer so as to form the patterned mask layer.

6. A method for manufacturing an array substrate, comprising:
a step S 100 of forming the gate electrode layer on the substrate by using the method of claim 5 .

7. The method according to claim 6 , after the step S 100 , further comprising:
a step S 200 of forming a gate insulating layer on the gate electrode layer and forming an active layer on the gate insulating layer.

8. The method according to claim 7 , wherein the step S 200 further comprises:
a step S 201 of forming the gate insulating layer on the gate electrode layer;
a step S 202 of forming an amorphous silicon layer on the gate insulating layer; and
a step S 203 of converting the amorphous silicon layer into a polysilicon layer served as the active layer by performing an Excimer Laser Annealing (ELA) process on the amorphous silicon layer.

9. A method for manufacturing an array substrate, comprising:
a step S 100 of forming the gate electrode layer on the substrate by using the method of claim 2 .

10. The method according to claim 9 , after the step S 100 , further comprising:
a step S 200 of forming a gate insulating layer on the gate electrode layer and forming an active layer on the gate insulating layer.

11. The method according to claim 10 , wherein the step S 200 further comprises:
a step S 201 of forming the gate insulating layer on the gate electrode layer;
a step S 202 of forming an amorphous silicon layer on the gate insulating layer; and
a step S 203 of converting the amorphous silicon layer into a polysilicon layer served as the active layer by performing an Excimer Laser Annealing (ELA) process on the amorphous silicon layer.

12. A method for manufacturing an array substrate, comprising:
a step S 100 of forming the gate electrode layer on the substrate by using the method of claim 1 .

13. The method according to claim 12 , after the step S 100 , further comprising:
a step S 200 of forming a gate insulating layer on the gate electrode layer and forming an active layer on the gate insulating layer.

14. The method according to claim 13 , wherein the step S 200 further comprises:
a step S 201 of forming the gate insulating layer on the gate electrode layer;
a step S 202 of forming an amorphous silicon layer on the gate insulating layer; and
a step S 203 of converting the amorphous silicon layer into a polysilicon layer served as the active layer by performing an Excimer Laser Annealing (ELA) process on the amorphous silicon layer.

15. The method according to claim 14 , wherein the gate insulating layer and the amorphous silicon layer are formed by Plasma Enhanced Chemical Vapor Deposition (PECVD) process.

16. A gate electrode, comprising: a gate electrode layer disposed on a substrate, wherein the substrate comprises a gate electrode region and a non-gate electrode region; the gate electrode layer comprises a conductive portion corresponding to the gate electrode region and a transparent portion corresponding to the non-gate electrode region, and the conductive portion has a thickness equal to a thickness of the transparent portion.

Assignees

• Boe Technology Group Co Ltd

Inventors

• Zhang Bin
• Liu Chienhung
• Chan Yucheng
• Sun Xuefei
• Zhou Tingting

Classifications

• H10P14/3456

  Polycrystalline · CPC title

• H10P95/90 Primary

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P14/6314

  of a metallic layer · CPC title

• H10D64/013 Primary

  of electrodes having a conductor capacitively coupled to a semiconductor by an insulator · CPC title

• H10D30/0321

  comprising silicon, e.g. amorphous silicon or polysilicon · CPC title