Method for fabricating array substrate, array substrate and display device

Patent metadata

Field	Value
Publication number	US-10224252-B2
Application number	US-201715736972-A
Country	US
Kind code	B2
Filing date	Jun 14, 2017
Priority date	Aug 10, 2016
Publication date	Mar 5, 2019
Grant date	Mar 5, 2019

Abstract

A method for fabricating an array substrate, an array substrate, and a display device are disclosed. The method includes forming a whole layer of opaque film on a substrate; treating the film to form a transparent region and an opaque region in the film, wherein the opaque region corresponds with a channel region of an active layer; and forming a thin film transistor on the film which has been treated. In the method, prior to forming the thin film transistor, the whole layer of opaque film is formed to comprise the transparent region and the opaque region. When other films are deposited on the whole layer of film, no difference in height occurs, and this further avoids various defects due to difference in height.

First claim

What is claimed is:

1. A method for fabricating an array substrate, comprising:
forming a whole layer of opaque film on a substrate;
treating the film to form a transparent region and an opaque region in the film, wherein the opaque region corresponds with a channel region of an active layer; and
forming a thin film transistor on the film which has been treated.

2. The method of claim 1 , wherein the step of treating the film to form the transparent region and the opaque region in the film comprises:
applying photoresist on the film;
performing exposure and development on the photoresist with a mask plate, and retaining the photoresist corresponding with an opaque region to be formed of the film;
oxidizing the film in a transparent region to be formed with an oxidant, by using the retained photoresist as a mask, so that the film in the transparent region to be formed is formed to be transparent; and
peeling off the retained photoresist to obtain the transparent region and the opaque region in the film.

3. The method of claim 2 , wherein the oxidant is hydrogen peroxide.

4. The method of claim 1 , wherein an orthogonal projection of the channel region of the active layer on the substrate falls within an orthogonal projection of the opaque region on the substrate.

5. The method of claim 1 , wherein the whole layer of opaque film comprises tantalum.

6. The method of claim 1 , wherein the step of forming the thin film transistor on the film which has been treated comprises:
depositing an amorphous silicon layer on the film which has been treated, and annealing the amorphous silicon layer with an excimer laser, so that the amorphous silicon layer is crystallized into a polycrystalline silicon layer; and
forming a pattern of the active layer by performing a patterning process on the polycrystalline silicon layer for one time.

7. An array substrate, comprising: a substrate, a whole layer of film which is arranged on the substrate, and a thin film transistor,
wherein the film comprises a transparent region and an opaque region, and the opaque region corresponds with a channel region of an active layer.

8. The array substrate of claim 7 , wherein an orthogonal projection of the channel region of the active layer on the substrate falls within an orthogonal projection of the opaque region on the substrate.

9. The array substrate of claim 7 , wherein the film in the transparent region is an oxidized film.

10. The array substrate of claim 9 , wherein the opaque region comprises tantalum, and the transparent region comprises tantalum oxide.

11. The array substrate of claim 8 , wherein the thin film transistor is of a top gate type.

12. The array substrate of claim 7 , further comprising: a buffer layer which is arranged between the film and the thin film transistor, wherein the buffer layer has a thickness of 1000 angstrom-5000 angstrom.

13. A display device, comprising the array substrate of claim 7 .

14. The method of claim 2 , wherein the step of forming the thin film transistor on the film which has been treated comprises:
depositing an amorphous silicon layer on the film which has been treated, and annealing the amorphous silicon layer with an excimer laser, so that the amorphous silicon layer is crystallized into a polycrystalline silicon layer; and
forming a pattern of the active layer by performing a patterning process on the polycrystalline silicon layer for one time.

15. The method of claim 3 , wherein the step of forming the thin film transistor on the film which has been treated comprises:
depositing an amorphous silicon layer on the film which has been treated, and annealing the amorphous silicon layer with an excimer laser, so that the amorphous silicon layer is crystallized into a polycrystalline silicon layer; and
forming a pattern of the active layer by performing a patterning process on the polycrystalline silicon layer for one time.

16. The method of claim 4 , wherein the step of forming the thin film transistor on the film which has been treated comprises:
depositing an amorphous silicon layer on the film which has been treated, and annealing the amorphous silicon layer with an excimer laser, so that the amorphous silicon layer is crystallized into a polycrystalline silicon layer; and
forming a pattern of the active layer by performing a patterning process on the polycrystalline silicon layer for one time.

17. The method of claim 5 , wherein the step of forming the thin film transistor on the film which has been treated comprises:
depositing an amorphous silicon layer on the film which has been treated, and annealing the amorphous silicon layer with an excimer laser, so that the amorphous silicon layer is crystallized into a polycrystalline silicon layer; and
forming a pattern of the active layer by performing a patterning process on the polycrystalline silicon layer for one time.

18. The array substrate of claim 8 , further comprising: a buffer layer which is arranged between the film and the thin film transistor, wherein the buffer layer has a thickness of 1000 angstrom-5000 angstrom.

19. The array substrate of claim 9 , further comprising: a buffer layer which is arranged between the film and the thin film transistor, wherein the buffer layer has a thickness of 1000 angstrom-5000 angstrom.

20. The array substrate of claim 10 , further comprising: a buffer layer which is arranged between the film and the thin film transistor, wherein the buffer layer has a thickness of 1000 angstrom-5000 angstrom.

Assignees

• Boe Technology Group Co Ltd

Inventors

• Zhang Bin
• Liu Chienhung
• Chan Yucheng
• Sun Xuefei
• Cao Zhanfeng

Classifications

• H01L27/14623

  Electricity · mapped topic

• H01L21/84 Primary

  Electricity · mapped topic

• H01L27/1218

  Electricity · mapped topic

• H01L27/1222

  Electricity · mapped topic

• H10D30/0321

  comprising silicon, e.g. amorphous silicon or polysilicon · CPC title