Constant Vds1 bias control for stacked transistor configuration

Patent metadata

Field	Value
Publication number	US-11128261-B2
Application number	US-201916264106-A
Country	US
Kind code	B2
Filing date	Jan 31, 2019
Priority date	Dec 28, 2012
Publication date	Sep 21, 2021
Grant date	Sep 21, 2021

Abstract

Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are presented, where the amplifier can have a varying supply voltage. According to one aspect, the gate of the input transistor of the amplifier is biased with a fixed voltage whereas the gates of the other transistors of the amplifier are biased with variable voltages that are linear functions of the varying supply voltage. According to another aspect, the linear functions are such that the variable voltages coincide with the fixed voltage at a value of the varying supply voltage for which the input transistor is at the edge of triode. According to another aspect, biasing of the stacked transistors is such that, while the supply voltage varies, the drain-to-source voltage of the input transistor is maintained to a fixed value whereas the drain-to-source voltages of all other transistors are equal to one another.

First claim

The invention claimed is:

1. A circuital arrangement comprising:
i) an amplifier comprising:
stacked transistors having a plurality of bias terminals comprising a plurality of gate terminals of the stacked transistors and a drain terminal of an output transistor of the stacked transistors;
an input port coupled to an input transistor of the stacked transistors;
an output port coupled to the drain terminal of the output transistor; and
a reference terminal coupling the input transistor to a reference potential,
wherein:
the stacked transistors comprise two subsets of transistors arranged in series, a first subset comprising the input transistor connected between the reference potential at the reference terminal and a second subset, the second subset comprising a plurality of transistors connected in series with each other, a last transistor of the plurality of transistors being the output transistor and a first transistor of the plurality of transistors connected in series with the input transistor, the second subset connected between the first subset and a variable supply voltage provided to the output transistor;

ii) a gate bias circuit,
wherein:
for a varying voltage of the variable supply voltage, the gate bias circuit provides:
a) a substantially fixed bias voltage to a gate of the first transistor so to maintain a substantially constant drain voltage of the input transistor, and
b) a respective variable bias voltage, that is a function of the variable supply voltage, to a gate of each transistor of the second subset except the first transistor, and

iii) a plurality of gate capacitors connected between gate terminals of respective transistors of the plurality of transistors and the reference potential,
wherein each gate capacitor of the plurality of gate capacitors is configured to allow a voltage at a gate terminal of a respective transistor to vary along with a radio frequency (RF) voltage at a drain of the respective transistor.

2. The circuital arrangement according to claim 1 , wherein the respective variable bias voltage controls a drain-to-source voltage of the each transistor of the second subset to be substantially equal to a drain-to-source voltage of any other transistor of the second subset.

3. The circuital arrangement according to claim 1 , wherein the respective variable bias voltage of the each transistor of the second subset provides a substantially equal distribution of a difference between the varying voltage of the variable supply voltage and the substantially constant drain voltage of the input transistor across drain-to-source voltages of transistors of the second subset.

4. The circuital arrangement according to claim 1 , wherein the respective variable bias voltage is a linear function of the variable supply voltage.

5. The circuital arrangement according to claim 1 , wherein the respective variable bias voltage and the substantially fixed bias voltage coincide at a value of the varying voltage that is in a range of +/−10% of a value of the varying voltage for which the input transistor is at an edge of triode.

6. The circuital arrangement according to claim 1 , wherein the respective variable bias voltage and the substantially fixed bias voltage coincide at a value of the varying voltage that is substantially equal to a value for which the input transistor is at an edge of triode.

7. The circuital arrangement according to claim 1 , wherein the respective variable bias voltage is a linear function of the variable supply voltage in a range of values equal to or larger than a value for which the input transistor is at an edge of triode.

8. The circuital arrangement according to claim 1 , wherein the respective variable bias voltage is generated via a circuit comprising two series-connected resistors that are coupled, at one end, to the variable supply voltage, and at another end, to a substantially fixed reference voltage.

9. The circuital arrangement according to claim 8 , wherein the substantially fixed bias voltage is generated via a circuit comprising two series-connected resistors that are coupled, at one end, to the substantially fixed reference voltage, and at another end, to the reference potential.

10. The circuital arrangement according to claim 1 , wherein the respective variable bias voltage is generated via a circuit comprising one or more of: a) a lookup table, b) a A/D converter, c) a D/A converter, and d) an operational amplifier.

11. The circuital arrangement according to claim 1 , wherein the variable supply voltage varies in a range from 1 volt to 5 volts.

12. The circuital arrangement according to claim 1 , wherein the variable supply voltage varies in a range from 2.5 volts to 4.8 volts.

13. The circuital arrangement according to claim 1 , wherein transistors of the first and second subsets of transistors are metal-oxide-semiconductor (MOS) field effect transistors (FETs), or complementary metal-oxide-semiconductor (CMOS) field effect transistors (FETs).

14. The circuital arrangement according to claim 11 , wherein said transistors are fabricated using one of: a) silicon-on-insulator (SOI) technology, and b) silicon-on-sapphire technology (SOS).

15. A circuital arrangement comprising:
an amplifier comprising an input transistor and a plurality of cascode transistors comprising a first cascode transistor coupled to the input transistor;
a biasing circuit configured to generate, based on a varying supply voltage to the amplifier, a fixed gate bias voltage for the first cascode transistor and a plurality of variable gate bias voltages for remaining transistors of the plurality of cascode transistors so to control the input transistor to maintain operation in saturation region while the plurality of cascode transistors operate with varying bias voltages, and
a plurality of gate capacitors connected between gate terminals of respective transistors of the plurality of cascode transistors and a reference potential,
a plurality of resistors connected between said gate terminals and the biasing circuit,
wherein each gate capacitor of the plurality of gate capacitors is configured to allow a voltage at a gate terminal of a respective transistor to vary along with a radio frequency (RF) voltage at a drain of the respective transistor, and
wherein the fixed gate bias voltage and the plurality of variable gate bias voltages are coupled to the first cascode and the remaining transistors through respective resistors of the plurality of resistors.

16. The circuital arrangement according to claim 15 , wherein each of the plurality of variable gate bias voltages is a linear function of the varying supply voltage that coincides with the fixed gate bias voltage at a value of the varying supply voltage for which the input transistor is at an edge of triode.

17. A method for biasing an amplifier, the method comprising:
providing an amplifier comprising an input transistor and a plurality of cascode transistors comprising a first cascode transistor coupled to the input transistor;
connecting a plurality of gate capacitors between gate terminals of respective transistors of the plurality of cascode transistors and a reference potential, thereby allowing a voltage at a gate terminal of a respective transistor to vary along with a radio frequency (RF) voltage at a drain of the respective transistor;
applying a variable supply voltage to the amplifier;
based on the applying, providing a fixed bias voltage to a gate of the first cascode transistor so to maintain a substantially constant drain voltage of the input transistor; and
bas

Assignees

• Psemi Corp

Inventors

• Ranta Tero Tapio
• Murphy Christopher C
• Dykstra Jeffrey A

Classifications

• H03F2200/102

  A non-specified detector of a signal envelope being used in an amplifying circuit · CPC title

• H03F2200/18

  the bias of the gate of a FET being controlled by a control signal · CPC title

• H03F1/3205

  in field-effect transistor amplifiers · CPC title

• H03F1/302

  in bipolar transistor amplifiers (H03F1/303, H03F1/305, H03F1/307 take precedence) · CPC title

• H03F3/213

  in integrated circuits · CPC title