Solid-state imaging device, method of manufacturing the same, and electronic apparatus

Patent metadata

Field	Value
Publication number	US-11127771-B2
Application number	US-201816169735-A
Country	US
Kind code	B2
Filing date	Oct 24, 2018
Priority date	Mar 11, 2013
Publication date	Sep 21, 2021
Grant date	Sep 21, 2021

Abstract

Solid-state imaging devices, methods of producing a solid-state imaging device, and electronic apparatuses are provided. More particularly, a solid-state image device includes a silicon substrate, and at least a first photodiode formed in the silicon substrate. The device also includes an epitaxial layer with a first surface adjacent a surface of the silicon substrate, and a transfer transistor with a gate electrode that extends from the at least a first photodiode to a second surface of the epitaxial layer opposite the first surface. In further embodiments, a solid-state imaging device with a plurality of pixels formed in a second semiconductor substrate wherein the pixels are symmetrical with respect to a center point is provided. A floating diffusion is formed in an epitaxial layer, and a plurality of transfer gate electrodes that are each electrically connected to the floating diffusion by one of the transfer gate electrodes is provided.

First claim

What is claimed:

1. An imaging device, comprising:
a first semiconductor layer having a first surface and a second surface opposite to the first surface, the first surface being a light incident side of the first semiconductor layer;
a photoelectric conversion region including a p-n junction disposed in the first semiconductor layer;
a first transistor including a first doped region, a second doped region, and a gate structure having a gate electrode, the first doped region and the second doped region of the first transistor being disposed at the second surface of the first semiconductor layer on opposite sides of the gate structure of the first transistor, wherein a channel region of the first transistor exists at the second surface of the first semiconductor layer between the first doped region and the second doped region of the first transistor;
a second semiconductor layer on the first semiconductor layer and having a third surface and a fourth surface opposite to the third surface, the third surface of the second semiconductor layer facing the second surface of the first semiconductor layer; and
a second transistor including a source, a drain, and a gate structure having a gate electrode, the source and drain of the second transistor being disposed at the fourth surface of the second semiconductor layer on opposite sides of the gate structure of the second transistor, wherein a channel region of the second transistor exists at the fourth surface of the second semiconductor layer between the source and the drain of the second transistor,
wherein the gate structure of the first transistor includes a first face and a second face opposite the first face, the first face of the gate structure of the first transistor being coplanar with the third surface of the second semiconductor layer.

2. The imaging device according to claim 1 , wherein the first transistor is a transfer transistor, and wherein the gate structure of the second transistor includes a first face and a second face opposite the first face, the second face of the gate structure of the second transistor being on the fourth surface of the second semiconductor layer.

3. The imaging device according to claim 1 , wherein the second transistor is an amplification transistor.

4. The imaging device according to claim 1 , wherein the gate electrode of the first transistor is disposed on the second surface of the first semiconductor layer.

5. The imaging device according to claim 1 , wherein the gate electrode of the second transistor is disposed on the fourth surface of the second semiconductor layer.

6. The imaging device according to claim 1 , wherein the second semiconductor layer has a p-type conductivity.

7. The imaging device according to claim 1 , further comprising first and second semiconductor regions with a p-type conductivity disposed on respective sides of the photoelectric conversion region in a cross-sectional view.

8. The imaging device according to claim 1 , further comprising an anti-reflection film disposed below the first surface of the first semiconductor layer.

9. The imaging device according to claim 1 , wherein the gate electrode of the first transistor is disposed on the second surface of the first semiconductor layer, and
wherein the gate electrode of the second transistor is disposed on the fourth surface of the second semiconductor layer.

10. The imaging device of claim 2 , wherein the second face of the gate structure of the first transistor is disposed closer to the first surface of the first semiconductor layer than the first face of the gate structure of the second electrode.

11. An electronic apparatus, comprising:
an optical system;
a signal processing circuit; and
an imaging device, comprising:
a first semiconductor layer having a first surface and a second surface opposite to the first surface, the first surface being a light incident side of the first semiconductor layer;
a photoelectric conversion region including a p-n junction disposed in the first semiconductor layer;
a first transistor including a first doped region, a second doped region, and a gate structure having a gate electrode, the first doped region and the second doped region of the first transistor being disposed at the second surface of the first semiconductor layer on opposite sides of the gate structure of the first transistor, wherein a channel region of the first transistor exists at the second surface of the first semiconductor layer between the first doped region and the second doped region of the first transistor;
a second semiconductor layer on the first semiconductor layer and having a third surface and a fourth surface opposite to the third surface, the third surface of the second semiconductor layer facing the second surface of the first semiconductor layer; and
a second transistor including a source, a drain, and a gate structure having a gate electrode, the source and the drain of the second transistor being disposed at the fourth surface of the second semiconductor layer on opposite sides of the gate structure of the second transistor, wherein a channel region of the second transistor exists at the fourth surface of the second semiconductor layer between the source and the drain of the second transistor,
wherein the gate structure of the first transistor includes a first face and a second face opposite the first face, the first face of the gate structure of the first transistor being coplanar with the third surface of the second semiconductor layer.

Assignees

• Sony Corp

Inventors

• Tanaka Yusuke
• Wakano Toshifumi
• Tatani Keiji
• Nagano Takashi
• Iwamoto Hayato
• Nakazawa Keiichi
• Hirano Tomoyuki
• Yamaguchi Shinpei
• Maruyama Shunsuke

Classifications

• H10F39/8063

  Microlenses · CPC title

• H10F39/8053

  Colour filters · CPC title

• H10F39/1825

  Multicolour image sensors having stacked structure, e.g. NPN, NPNPN or multiple quantum well [MQW] structures · CPC title

• H10F39/813

  Electronic components shared by multiple pixels, e.g. one amplifier shared by two pixels · CPC title

• H10F39/80373

  characterised by the gate of the transistor · CPC title