Structure of semiconductor device and method for fabricating the same

Patent metadata

Field	Value
Publication number	US-11127752-B2
Application number	US-202016798126-A
Country	US
Kind code	B2
Filing date	Feb 21, 2020
Priority date	Feb 21, 2020
Publication date	Sep 21, 2021
Grant date	Sep 21, 2021

Abstract

A semiconductor device includes a substrate, having cell region and high-voltage region. A memory cell is on the substrate within the cell region. The memory cell includes a memory gate structure and a selection gate structure on the substrate. A first spacer is sandwiched between or respectively on sidewalls of the memory cell structure and the selection gate structure. First high-voltage transistor is on the substrate within the high-voltage region. A first composite gate structure of the first high-voltage transistor includes a first gate structure on the substrate, an insulating layer with a predetermined thickness on the substrate in a -like structure or an L-like structure at cross-section, and a second gate structure on the insulating layer along the -like structure or the L-like structure. The selection gate structure and the second gate structure are originated from a same preliminary conductive layer.

First claim

What is claimed is:

1. A structure of semiconductor device, comprising:
a substrate, configured to have a cell region and a high-voltage region;
a memory cell, on the substrate within the cell region, the memory cell including:
a memory gate structure on the substrate;
a selection gate structure on the substrate; and
a first spacer, sandwiched between or respectively on sidewalls of the memory cell structure and the selection gate structure; and

a first high-voltage transistor, on the substrate within the high-voltage region, a first composite gate structure of the first high-voltage transistor including:
a first gate structure on the substrate;
an insulating layer with a predetermined thickness on the substrate in -like structure or an L-like structure at cross-section; and
a second gate structure on the insulating layer along the -like structure or the L-like structure,

wherein the insulating layer and the first spacer are originated from a same preliminary dielectric layer,
wherein the selection gate structure and the second gate structure are originated from a same preliminary conductive layer.

2. The structure of semiconductor device in claim 1 , further comprising a second spacer on outer sidewall of the selection gate structure or on the first spacer, on a sidewall of the insulating layer with the second gate structure and on a sidewall of the first gate structure.

3. The structure of semiconductor device in claim 1 , wherein a length of a bottom horizontal portion of the -like structure or the L-like structure is set by a predetermined value.

4. The structure of semiconductor device in claim 1 , wherein the insulating layer of the high-voltage transistor is directly sandwiched between the first gate structure and the second gate structure.

5. The structure of semiconductor device in claim 1 , wherein the insulating layer of the high-voltage transistor is the -like structure, and a top horizontal portion of the -like structure is overlapping with the first gate structure.

6. The structure of semiconductor device in claim 5 , wherein the first gate structure includes a partial mask at top of the first gate structure and under the top horizontal portion of the insulating layer.

7. The structure of semiconductor device in claim 1 , wherein the insulating layer of the high-voltage transistor is the L-like structure, and a vertical portion of the L-like structure is directly sandwiched between the first gate structure and the second gate structure.

8. The structure of semiconductor device in claim 1 , wherein the memory gate structure comprises an oxide/nitride/oxide (ONO) layer and a conductive gate layer, sacked on the substrate, the selection gate is adjacent to the memory gate structure.

9. The structure of semiconductor device in claim 1 , further comprising a second high-voltage transistor having a second composite gate structure being symmetrical to the first composite gate structure, wherein a region of the substrate between the first composite gate structure and the second composite gate structure comprises doped consecutive regions of N-type, P-type and N-type (NPN) or P-type, N-type and P-type (PNP).

10. The structure of semiconductor device in claim 9 , further comprising:
a first-type doped region under each of the first composite gate structure and the second composite gate structure; and
a second-type doped region between the two first-type doped regions under the doped region of NPN or PNP.

11. A structure of semiconductor device, comprising:
a substrate, configured to have a cell region and a high-voltage region;
a memory cell, on the substrate within the cell region, the memory cell including:
a memory gate structure on the substrate;
a selection gate structure on the substrate; and
a first spacer, sandwiched between or respectively on sidewalls of the memory cell structure and the selection gate structure; and

a first high-voltage transistor, on the substrate within the high-voltage region, a first composite gate structure of the first high-voltage transistor including:
a first gate structure on the substrate;
an insulating layer with a predetermined thickness on the substrate in a -like structure or an L-like structure at cross-section; and
a second gate structure on the insulating layer along the -like structure or the L-like structure,

wherein the selection gate structure and the second gate structure are originated from a same preliminary conductive layer.

12. A method for fabricating semiconductor device, comprising:
providing a substrate, configured to have a cell region and a high-voltage region;
forming a memory cell on the substrate within the cell region, the memory cell including:
a memory gate structure on the substrate;
a selection gate structure on the substrate; and
a first spacer, sandwiched between or respectively on sidewalls of the memory cell structure and the selection gate structure; and

forming a first high-voltage transistor, on the substrate within the high-voltage region, wherein a first composite gate structure of the first high-voltage transistor as formed includes:
a first gate structure on the substrate;
an insulating layer with a predetermined thickness on the substrate in -like structure or an L-like structure at cross-section,
a second gate structure on the insulating layer along the -like structure or the L-like structure;
wherein the insulating layer and the first spacer are formed from a same preliminary dielectric layer or from different preliminary dielectric layers,
wherein the selection gate structure and the second gate structure are originated from a same preliminary conductive layer.

13. The method for fabricating semiconductor device in claim 12 , further comprising forming a second spacer on outer sidewall of the selection gate structure or on the first spacer, on a sidewall of the insulating layer with the second gate structure and on a sidewall of the first gate structure.

14. The method for fabricating semiconductor device in claim 12 , wherein a length of a bottom horizontal portion of the -like structure or the L-like structure is set to a predetermined value by a patterning process.

15. The method for fabricating semiconductor device in claim 12 , wherein the insulating layer of the high-voltage transistor as formed is directly sandwiched between the first gate structure and the second gate structure.

16. The method for fabricating semiconductor device in claim 12 , wherein the insulating layer of the high-voltage transistor as formed is the -like structure, and a top horizontal portion of the -like structure is overlapping with the first gate structure.

17. The method for fabricating semiconductor device in claim 16 , wherein the first gate structure as formed includes a partial mask at top of the first gate structure and under the top horizontal portion of the insulating layer.

18. The method for fabricating semiconductor device in claim 12 , wherein the insulating layer of the high-voltage transistor as formed is the L-like structure, and a vertical portion of the L-like structure is directly sandwiched between the first gate structure and the second gate structure.

19. The method for fabricating semiconductor device in claim 12 , wherein the memory gate structure as formed comprises an oxide/nitride/oxide (ONO) layer and a conductive gate layer, sacked on the substrate, the selection gate is adjacent to the memory gate structure.

20. The method for fabricating semiconductor device in

Assignees

• United Microelectronics Corp

Inventors

• Hsu Chia-Ching
• Xiang Wang
• Wang Shen-De
• Huang Chun-Sung

Classifications

• H10W10/051

  of isolation region based on field-effect · CPC title

• H10W10/50

  Isolation regions based on field-effect · CPC title

• H10D64/516

  the thicknesses being non-uniform · CPC title

• H10D64/111

  Field plates · CPC title

• H10D64/037

  comprising charge-trapping insulators · CPC title