Gate driving circuit and a display device including the gate driving circuit

Patent metadata

Field	Value
Publication number	US-10109252-B2
Application number	US-201815964249-A
Country	US
Kind code	B2
Filing date	Apr 27, 2018
Priority date	Jan 21, 2015
Publication date	Oct 23, 2018
Grant date	Oct 23, 2018

Abstract

A gate driving circuit includes driving stages. Each of the driving stages applies each of gate signals to each of gate lines of a display panel. A k-th (k is a natural number equal to or greater than 2) driving stage includes a first output transistor, a capacitor, and first and second control transistor. The first output transistor includes a control electrode connected to a first node, an input electrode receiving a clock signal, and an output electrode outputting a k-th gate signal. The capacitor is connected between the output electrode of the first output transistor and the control electrode of the first output transistor. The first control transistor applies a first control signal to a second node to control a voltage of the first node before the k-th gate signal is output. The second control transistor is diode-connected between the second node and the first node.

First claim

What is claimed is:

1. A gate driving circuit comprising:
a plurality of driving stages, each of which applies a corresponding one of gate signals to a corresponding one of gate lines of a display panel, wherein a k-th (k is a natural number equal to or greater than 2) driving stage among the driving stages comprises:
a first output transistor comprising a control electrode connected to a first node, an input electrode receiving a clock signal, and an output electrode outputting a k-th gate signal generated on the basis of the clock signal;
a capacitor connected between the output electrode of the first output transistor and the control electrode of the first output transistor;
a first control transistor comprising a control electrode receiving a signal output from a (k−1)-th driving stage, an input electrode receiving a bias voltage, and an output electrode outputting a first control signal, the first control transistor applying the first control signal to a second node to control a voltage of the first node before the k-th gate signal is output; and
a second control transistor including input and control electrodes commonly connected to the second node, and an output electrode connected to the first node such that a current path is formed between the second node and the first node,
wherein a second control signal synchronized with the k-th gate signal is applied to the second node after the first control signal is applied to the second node.

2. The gate driving circuit of claim 1 , wherein the signal output from the (k−1)-th driving stage corresponds to a (k−1)-th carry signal output from the (k−1)-th driving stage, and the bias voltage is substantially the same as a high level of the (k−1)-th carry signal.

3. The gate driving circuit of claim 2 , further comprising a second output transistor comprising a control electrode connected to the first node, an input electrode receiving the clock signal, and an output electrode outputting a k-th carry signal generated on the basis of the clock signal.

4. The gate driving circuit of claim 3 , wherein the second control signal corresponds to the k-th carry signal output from the k-th driving stage.

5. The gate driving circuit of claim 3 , further comprising a third control transistor comprising control and input electrodes commonly receiving the k-th carry signal, and an output electrode outputting the second control signal.

6. A gate driving circuit comprising:
a plurality of driving stages, each of which applies a corresponding one of gate signals to a corresponding one of gate lines of a display panel,
wherein a k-th (k is a natural number equal to or greater than 2) driving stage among the driving stages comprises:
an output part outputting a k-th gate signal through a k-th output node and a k-th carry signal through a k-th carry node in response to a voltage of a first node, wherein the k-th gate signal and the k-th carry signal are generated on the basis of a clock signal;
a control part controlling the voltage of the first node;
an inverter part outputting a switching signal generated on the basis of the clock signal; and
a pull-down part pulling down voltages of the k-th output node and the k-th carry node,
wherein the control part comprises:
a first control transistor comprising a control electrode receiving a (k−1)-th carry signal output from a (k−1)-th driving stage, an input electrode receiving a bias voltage having a same level as a high level of the (k−1)-th carry signal, and an output electrode outputting a first control signal, the first control transistor applying the first control signal to a second node to control a voltage of the first node before the k-th gate signal is output;
a second control transistor comprising control and input electrodes commonly connected to the second node, and an output electrode connected to the first node; and
a third control transistor comprising control and input electrodes commonly receiving the k-th carry signal, and an output electrode connected to the second node.

Assignees

• Samsung Display Co Ltd

Inventors

• Cho Duc-Han
• Kim Beomjun
• Kim Yoonho
• Takeuchi Noboru
• Kim Kangnam

Classifications

• G11C19/28

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title

• G11C19/184

  with field-effect transistors, e.g. MOS-FET · CPC title

• G09G3/3677 Primary

  suitable for active matrices only · CPC title

• G09G3/3614

  Control of polarity reversal in general · CPC title

• G09G3/28

  using luminous gas-discharge panels, e.g. plasma panels · CPC title