Coherent placement of slotline mode suppression structures in coplanar waveguides for quantum devices

Patent metadata

Field	Value
Publication number	US-11126776-B2
Application number	US-202016840930-A
Country	US
Kind code	B2
Filing date	Apr 6, 2020
Priority date	Jul 19, 2018
Publication date	Sep 21, 2021
Grant date	Sep 21, 2021

Abstract

A system includes a memory that stores computer executable components, and a processor executes the computer executable components stored in the memory. The computer executable components comprise: an assessment component that determines locations for mode suppression structures on a coplanar waveguide of a quantum chip having qubits; a simulation component that simulates performance of the quantum chip based on a subset of the locations for the mode suppression structures and parameters of the quantum chip, and generates a mode suppression structures placement model. A template component generates a template of specific coordinates for placement of a subset of the mode suppression structures on the quantum chip based on the mode suppression structures placement model; and a driver component employs the template to drive an auto-bonder to install the subset of the mode suppression structures on the quantum chip at the specific coordinates.

First claim

What is claimed is:

1. A system, comprising:
a memory that stores computer executable components;
a processor that executes the computer executable components stored in the memory, wherein the computer executable components comprise:
a template component that generates a template that defines specific coordinates for placement of mode suppression structures on a coplanar waveguide of a quantum chip based on a mode suppression structures placement model; and
a driver component that employs the template to drive an auto-bonder to install the mode suppression structures on the coplanar waveguide of the quantum chip at the specific coordinates.

2. The system of claim 1 , wherein the specific coordinates based on the mode suppression structures placement model comprises distances between the mode suppression structures as a function of frequency of qubits of the quantum chip.

3. The system of claim 1 , wherein the specific coordinates based on the mode suppression structures placement model are selected to suppress slot line modes.

4. The system of claim 1 , wherein the specific coordinates based on the mode suppression structures placement model are selected to mitigate crosstalk.

5. The system of claim 1 , wherein the specific coordinates based on the mode suppression structures placement model are selected to mitigate resonator losses.

6. The system of claim 1 , wherein the specific coordinates based on the mode suppression structures placement model are selected as a function of rules associated with properties of the mode suppression structures, the coplanar waveguide, and the quantum chip.

7. The system of claim 1 , wherein the template component generates the template in a graphic database system (GDS) file format.

8. A computer-implemented method, comprising:
generating, by a device operatively coupled to a processor, a template that defines specific coordinates for placement of mode suppression structures on a coplanar waveguide of a quantum chip based on a mode suppression structures placement model; and
employing, by the device, the template to drive an auto-bonder to install the mode suppression structures on the coplanar waveguide of the quantum chip at the specific coordinates.

9. The computer-implemented method of claim 8 , wherein the specific coordinates based on the mode suppression structures placement model comprises distances between the mode suppression structures as a function of frequency of qubits of the quantum chip.

10. The computer-implemented method of claim 8 , wherein the specific coordinates based on the mode suppression structures placement model are selected to suppress slot line modes.

11. The computer-implemented method of claim 8 , wherein the specific coordinates based on the mode suppression structures placement model are selected to mitigate crosstalk.

12. The computer-implemented method of claim 8 , wherein the specific coordinates based on the mode suppression structures placement model are selected to mitigate resonator losses.

13. The computer-implemented method of claim 8 , wherein the specific coordinates based on the mode suppression structures placement model are selected as a function of rules associated with properties of the mode suppression structures, the coplanar waveguide, and the quantum chip.

14. The computer-implemented method of claim 8 , wherein the template is in a graphic database system (GDS) file format.

15. A computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by processor to cause the processor to:
generate a template that defines specific coordinates for placement of mode suppression structures on a coplanar waveguide of a quantum chip based on a mode suppression structures placement model; and
employ the template to drive an auto-bonder to install the mode suppression structures on the coplanar waveguide of the quantum chip at the specific coordinates.

16. The computer program product of claim 15 , wherein the specific coordinates based on the mode suppression structures placement model comprises distances between the mode suppression structures as a function of frequency of qubits of the quantum chip.

17. The computer program product of claim 15 , wherein the specific coordinates based on the mode suppression structures placement model are selected to suppress slot line modes.

18. The computer program product of claim 15 , wherein the specific coordinates based on the mode suppression structures placement model are selected to mitigate crosstalk.

19. The computer program product of claim 15 , wherein the specific coordinates based on the mode suppression structures placement model are selected to mitigate resonator losses.

20. The computer program product of claim 15 , wherein the specific coordinates based on the mode suppression structures placement model are selected as a function of rules associated with properties of the mode suppression structures, the coplanar waveguide, and the quantum chip.

Assignees

• IBM

Inventors

• Olivadese Salvatore Bernardo
• Adiga Vivekananda P
• Hertzberg Jared Barney

Classifications

• G06F30/392 Primary

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• G06F30/3308

  using simulation · CPC title

• G06F30/20

  Design optimisation, verification or simulation (optimisation, verification or simulation of circuit designs G06F30/30) · CPC title

• G06F2119/10

  Noise analysis or noise optimisation · CPC title

• G06N10/00

  Quantum computing, i.e. information processing based on quantum-mechanical phenomena · CPC title