Codeword rotation for zone grouping of media codewords

Patent metadata

Field	Value
Publication number	US-11119946-B2
Application number	US-201916414771-A
Country	US
Kind code	B2
Filing date	May 16, 2019
Priority date	May 16, 2019
Publication date	Sep 14, 2021
Grant date	Sep 14, 2021

Abstract

Methods, systems, and devices for codeword rotation for zone grouping of media codewords are described. A value of a first pointer may be configured to correspond to a first memory address within a region of memory and a value of a second pointer may be configured to correspond to a second memory address within the region of memory. The method may include monitoring access commands for performing access operations within the region of memory, where the plurality of access command may be associated with requested addresses within the region of memory. The method may include updating the value of the second pointer bases on a quantity of the commands that are monitored satisfying a threshold and executing the plurality of commands on locations within the region of memory. The locations may be based on the requested address, the value of the first pointer, and the value of the second pointer.

First claim

What is claimed is:

1. A method, comprising:
configuring a first value of a first pointer to correspond to a first memory address within a region of memory and a second value of a second pointer to correspond to a second memory address within the region of memory;
monitoring a plurality of commands for performing access operations within the region of memory, the plurality of commands associated with requested addresses within the region of memory;
updating the second pointer from the second value to a third value based at least in part on a quantity of the plurality of commands that are monitored satisfying a threshold;
updating the first pointer from the first value to a fourth value based at least in part on a correspondence between the third value of the second pointer and the first value of the first pointer; and
executing the plurality of commands on a set of locations within the region of memory, the set of locations based at least in part on the requested addresses, the fourth value of the first pointer, and the third value of the second pointer.

2. The method of claim 1 , further comprising:
copying, based at least in part on updating the second pointer from the second value to the third value, a codeword from a memory location corresponding to the third value of the second pointer to a memory location corresponding to a previous value of the second pointer.

3. The method of claim 1 , wherein monitoring the plurality of commands further comprises:
tracking an access count associated with the plurality of commands executed at the region of memory, wherein updating the second pointer is based at least in part on the access count satisfying the threshold.

4. The method of claim 3 , wherein tracking the access count comprises:
increasing a value associated with the access count by a first factor for each read command executed at the region of memory and a second factor for each write command executed at the region of memory.

5. The method of claim 3 , further comprising:
resetting the access count each time the access count satisfies the threshold;
updating a value of the second pointer each time the access count satisfies the threshold; and
copying a codeword from a memory location corresponding to the updated value of the second pointer to a memory location corresponding to a previous value of the second pointer each time the access count satisfies the threshold.

6. The method of claim 1 , wherein:
updating the second pointer from the second value to the third value comprises decrementing the second pointer; and
updating the first pointer from the first value to the fourth value comprises incrementing the first pointer.

7. The method of claim 1 , wherein updating the first pointer from the first value to the fourth value is based at least in part on the first value of the first pointer coinciding with the updated third value of the second pointer.

8. The method of claim 1 , wherein:
the region of memory comprises at least one extra memory address that is external to an addressable address space for the plurality of commands; and
configuring the second value of the second pointer comprises assigning the second value of the second pointer to the at least one extra memory address.

9. The method of claim 1 , wherein each memory address of the region of memory is associated with a different codeword.

10. The method of claim 1 , wherein executing the plurality of commands comprises:
determining offset memory addresses for performing accesses within the region of memory based at least on part on the requested addresses of the plurality of commands, the first pointer, and relationships of the requested addresses to the first pointer and the second pointer.

11. A device, comprising:
a memory region associated with a plurality of memory addresses;
a memory interface coupled with the memory region and operable to receive address access commands from a host device;
circuitry coupled with the memory region and the memory interface and operable to:
set a first pointer to a first value corresponding to a first memory address within the memory region and a second pointer to a second value corresponding to a second memory address within the memory region;
monitor a plurality of commands for performing access operations within the memory region, the plurality of commands associated with requested addresses within the memory region;
update the second pointer from the second value to a third value based at least in part on a quantity of the plurality of commands that are monitored satisfying a threshold;
update the first pointer from the first value to a fourth value based at least in part on a correspondence between the third value of the second pointer and the first value of the first pointer; and
access the memory region based at least in part on the plurality of commands, the fourth value of the first pointer, and the third value of the second pointer.

12. The device of claim 11 , wherein the circuitry is further operable to:
copy, based at least in part on updating the second pointer from the second value to the third value, a codeword from a memory location corresponding to the third value to a memory location corresponding to the second value.

13. The device of claim 11 , wherein the circuitry is further operable to:
track an access count associated with accesses of the memory region; and
update the second pointer from the second value to the third value based at least in part on the access count satisfying the threshold.

14. The device of claim 13 , wherein:
operating the circuitry to track the access count comprises increasing a value associated with the access count by a first factor for each read access within the memory region and a second factor for each write access within the memory region.

15. The device of claim 13 , wherein the circuitry is further operable to:
reset the access count each time the access count satisfies the threshold;
update the second pointer each time the access count satisfies the threshold; and
copy a codeword from a memory location corresponding to a value of the updated second pointer to a memory location corresponding to a previous value of the second pointer each time the access count satisfies the threshold.

16. The device of claim 11 , wherein the circuitry is further operable to:
translate, for each of the plurality of commands, the requested address to an access address based at least on part on a value of the first pointer and a relationship of the requested address to a function of the value of the first pointer and a value of the second pointer.

17. The device of claim 16 , wherein the function of the value of the first pointer and the value of the second pointer comprises a modulo operation of the value of the first pointer subtracted from the value of the second pointer and a size of the memory region.

18. A method, comprising:
configuring a value of a first pointer to correspond to a first memory address within a region of memory and a value of a second pointer to correspond to a second memory address within the region of memory;
receiving a first plurality of commands for performing access operations within the region of memory;
determining that a quantity of the first plurality of commands satisfies a threshold;
updating the value of the second pointer to correspond to a third memory address within the region of memory based at least in part on the determining;
copying, based at least in part on updating the value of the second pointer, a codeword from the th

Assignees

• Micron Technology Inc

Inventors

• Pawlowski Joseph Thomas

Classifications

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• G06F12/10 Primary

  Address translation · CPC title

• G06F2212/1036

  Life time enhancement · CPC title

• G06F12/0238

  Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory · CPC title

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title