Memory system and SoC including linear addresss remapping logic

Patent metadata

Field	Value
Publication number	US-9256531-B2
Application number	US-201313803269-A
Country	US
Kind code	B2
Filing date	Mar 14, 2013
Priority date	Jun 19, 2012
Publication date	Feb 9, 2016
Grant date	Feb 9, 2016

Abstract

A system-on-chip is connected to a first memory device and a second memory device. The system-on-chip comprises a memory controller configured to control an interleaving access operation on the first and second memory devices. A modem processor is configured to provide an address for accessing the first or second memory devices. A linear address remapping logic is configured to remap an address received from the modem processor and to provide the remapped address to the memory controller. The memory controller performs a linear access operation on the first or second memory device in response to receiving the remapped address.

First claim

What is claimed is:

1. A system-on-chip connected to a first memory device and a second memory device, comprising:
a memory controller configured to control an interleaving access operation on the first and second memory devices;
a modem processor configured to provide an original address for accessing the first or second memory device; and
a linear address remapping logic configured to remap the original address received from the modem processor, configured to generate a remapped address, and configured to provide the remapped address to the memory controller,
wherein the memory controller performs a linear access operation on the first or second memory device in response to receiving the remapped address,
wherein the remapped address is partitioned into an interleaving access area and a linear access area,
the remapped address includes interleaving access area bits indicating an address in an address range where an interleaving access operation is to be performed, and linear access area bits indicating an address in an address range where a linear access operation is to be performed, and a remapping operation performed by the linear address remapping logic is accomplished by moving a location of a most significant bit of the linear access area bits to a less significant bit of the linear access area bits of the remapped address.

2. The system-on-chip of claim 1 , wherein the linear address remapping logic is configured to receive the original address from the modem processor, and configured to remap the original address from the modem processor selectively in response to a control signal.

3. The system-on-chip of claim 1 , wherein the linear address remapping logic determines whether the original address input from the modem processor belongs to the linear access area, based on a base address and a size of the linear access area.

4. The system-on-chip of claim 3 , wherein the linear address remapping logic decides the original address input from the modem processor to belong to the linear access area when the original address input from the modem processor is equal to or greater than the base address of the linear access area and less than a sum of the base address and the size of the linear access area.

5. The system-on-chip of claim 3 , wherein the linear address remapping logic decides the original address input from the modem processor to belong to the interleaving access area when the original address input from the modem processor is either less than the base address of the linear access area or equal to or greater than a sum of the base address and the size of the linear access area.

6. A method of accessing first and second memory devices connected to a system-on-chip, comprising:
receiving an original address for accessing the first or second memory device from a modem processor of the system-on-chip;
determining whether the original address corresponds to an interleaving access area or to a linear access area;
generating a remapped address by remapping the original address; and
performing a linear access operation or an interleaving access operation on the first and second memory devices according to the determination result and/or according to the remapped address, wherein the remapped-address is partitioned into an interleaving access area and a linear access area,
the remapped address includes interleaving access area bits indicating an address in an address range where an interleaving access operation is to be performed, and linear access area bits indicating an address in an address range where a linear access operation is to be performed, and
the remapping the original address includes moving a location of a most significant bit of the linear access area bits to a less significant bit of the linear access area bits of the remapped address.

7. The method of claim 6 , further comprising determining whether the original address input from the modem processor belongs to the linear access area, based on a base address and a size of the linear access area.

8. A memory system, comprising:
a first memory device and a second memory device;
a memory controller configured to control an interleaving access operation on the first and second memory devices;
a modem processor configured to provide an original address for accessing the first or second memory device; and
a linear address remapping logic configured to remap the original address received from the modem processor, configured to generate a remapped address, and configured to provide the remapped address to the memory controller,
wherein the memory controller performs a linear access operation on the first or second memory device in response to receiving the remapped address,
the remapped address is partitioned into an interleaving access area and a linear access area,
the remapped address includes interleaving access area bits indicating an address in an address range where the interleaving access operation is to be performed, and linear access area bits indicating an address in an address range where the linear access operation is to be performed, and
a remapping operation performed by the linear address remapping logic is performed by moving a location of a most significant bit of the linear access area bits to a less significant bit of the linear access area bits of the remapped address.

9. The memory system of claim 8 , wherein the linear address remapping logic determines whether the original address input from the modem processor belongs to the linear access area, based on a base address and a size of the linear access area.

10. The memory system of claim 9 , wherein the linear address remapping logic decides the original address input from the modem processor to belong to the linear access area when the original address input from the modem processor is equal to or greater than the base address of the linear access area and less than a sum of the base address and the size of the linear access area.

11. The memory system of claim 9 , wherein the linear address remapping logic decides the original address input from the modem processor to belong to the interleaving access area when the original address input from the modem processor is either less than the base address of the linear access area or equal to or greater than a sum of the base address and the size of the linear access area.

12. The memory system of claim 8 , wherein the linear access area comprises one or more linear access areas.

13. The memory system of claim 8 , wherein the memory system further comprises a central processing unit, and wherein the central processing unit, the memory controller, the modem processor, and the linear address remapping logic are implemented on a system-on-chip.

14. The memory system of claim 8 , wherein the memory system further comprises a central processing unit, and wherein the central processing unit, the memory controller, and the linear address remapping logic are implemented on a system-on-chip and wherein the modem processor is implemented on a modem device.

15. A system-on-chip (SoC) connected to a first memory device and a second memory device, comprising:
a memory controller configured to control an interleaving access operation on the first and second memory devices;
a modem processor configured to provide an original address for accessing the first or second memory device; and
a linear address remapping logic configured to receive the original address from the modem processor, configured to remap the original address received from the modem processor, configured to generate a remapped address, and configured to provide the rem

Assignees

• Samsung Electronics Co Ltd

Inventors

• Cho Dongsik

Classifications

• G06F13/4282

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• G06F3/0673

  Single storage device · CPC title

• G06F12/0607 Primary

  Interleaved addressing · CPC title

• G06F2212/1024

  Latency reduction · CPC title

• G06F15/781

  On-chip cache; Off-chip memory · CPC title