Error cache system with coarse and fine segments for power optimization

Patent metadata

Field	Value
Publication number	US-11119936-B2
Application number	US-201916598647-A
Country	US
Kind code	B2
Filing date	Oct 10, 2019
Priority date	Sep 27, 2016
Publication date	Sep 14, 2021
Grant date	Sep 14, 2021

Abstract

A memory device for storing data comprises a memory bank comprising a plurality of addressable memory cells, wherein the memory bank is divided into a plurality of segments. The memory device also comprises a cache memory operable for storing a second plurality of data words, wherein further each data word of the second plurality of data words is either awaiting write verification or is to be re-written into the memory bank. The cache memory is divided into a plurality of primary segments, wherein each primary segment of the cache memory is direct mapped to a corresponding segment of the plurality of segments of the memory bank, wherein each primary segment of the plurality of primary segments of the cache memory is sub-divided into a plurality of secondary segments, and each of the plurality of secondary segments comprises at least one counter for tracking a number of valid entries stored therein.

First claim

We claim:

1. A memory device for storing data, the memory device comprising:
a memory bank comprising a plurality of addressable memory cells, wherein the memory bank is divided into a plurality of segments;
a pipeline configured to process write operations of a first plurality of data words addressed to the memory bank; and
a cache memory operable for storing a second plurality of data words and associated memory addresses, wherein the second plurality of data words are a subset of the first plurality of data words, wherein the cache memory is associated with the memory bank and wherein further each data word of the second plurality of data words is either awaiting write verification associated with the memory bank or is to be re-written into the memory bank, wherein the cache memory is divided into a plurality of primary segments, wherein each primary segment of the cache memory is direct mapped to a corresponding segment of the plurality of segments of the memory bank, wherein each primary segment of the plurality of primary segments of the cache memory is sub-divided into a plurality of secondary segments, and each of the plurality of secondary segments comprises at least one counter for tracking a number of valid entries stored therein, and wherein a secondary segment for storing a data word from the second plurality of data words is selected based on a selection criterion.

2. The memory device of claim 1 , wherein a number of the plurality of primary segments is a power of 2.

3. The memory device of claim 1 , wherein each of the plurality of primary segments comprises a same number of secondary segments.

4. The memory device of claim 1 , wherein a number of total entries in a primary segment of the plurality of primary segments is a non power of 2.

5. The memory device of claim 1 , wherein a number of secondary segments in each of the plurality of primary segments is a non power of 2.

6. The memory device of claim 1 , wherein each secondary segment is associated with two respective counters to track a number of valid entries corresponding to write 1 errors and a number of valid entries corresponding to write 0 errors stored therein.

7. The memory device of claim 1 , wherein the memory bank comprises a plurality of magnetic random access memory (MRAM) cells.

8. The memory device of claim 1 , wherein the memory bank comprises a plurality of spin-transfer torque magnetic random access memory (STT-MRAM) cells.

9. A memory device for storing data, the memory device comprising:
a plurality of memory banks, each comprising a plurality of addressable memory cells, wherein each of the plurality of memory banks is divided into a plurality of segments;
a pipeline configured to process write operations of a first plurality of data words addressed to the plurality of memory banks; and
a cache memory operable for storing a second plurality of data words and associated memory addresses, wherein the second plurality of data words are a subset of the first plurality of data words, wherein the cache memory is associated with the plurality of memory banks and wherein further each data word of the second plurality of data words is either awaiting write verification associated with a bank from the plurality of memory banks or is to be re-written into a bank from the plurality of memory banks, wherein the cache memory is divided into a plurality of primary segments, wherein each primary segment of the cache memory is direct mapped to a corresponding segment of the plurality of segments of the plurality of memory banks, wherein each primary segment of the plurality of primary segments of the cache memory is sub-divided into a plurality of secondary segments, wherein each of the plurality of secondary segments comprises at least one counter for tracking a number of valid entries stored therein, and wherein a secondary segment from the plurality of secondary segments is selected for performing an access operation based on a selection criterion.

10. The memory device of claim 9 , wherein each of the plurality of primary segments comprises an equal number of secondary segments.

11. The memory device of claim 9 , wherein each secondary segment is associated with two respective counters to track of a number of valid entries corresponding to write 1 errors and a number of valid entries corresponding to write 0 errors stored therein.

12. The memory device of claim 9 , wherein the memory bank comprises a plurality of magnetic random access memory (MRAM) cells.

13. The memory device of claim 9 , wherein the memory bank comprises a plurality of spin-transfer torque magnetic random access memory (STT-MRAM) cells.

14. A memory device comprising:
a memory bank comprising a plurality of magnetic random access memory (MRAM) cells, wherein each memory cell is configured to store a data word at a respective one of a plurality of memory addresses, and wherein the memory bank is divided into a plurality of segments;
a dynamic redundancy register comprising data storage elements, wherein the dynamic redundancy register is divided into a plurality of primary segments, wherein each primary segment of the dynamic redundancy register is direct mapped to a corresponding segment of the plurality of segments of the memory bank, wherein each primary segment of the plurality of primary segments of the dynamic redundancy register is sub-divided into a plurality of secondary segments, and wherein each of the plurality of secondary segments comprises at least one counter for tracking a number of entries in a respective secondary segment; and
a pipeline bank coupled to the memory bank and the dynamic redundancy register, wherein the pipeline bank is configured to:
write a data word into a segment of the memory bank that corresponds to a selected address of the plurality of memory addresses;
verify the data word written into the memory bank to determine whether the data word was successfully written; and
responsive to a determination that the data word was not successfully written, writing the data word and the selected address into a selected secondary segment of a selected primary segment of the dynamic redundancy register, wherein the selected primary segment directly maps to the segment of the memory bank associated with the selected address of the data word, and wherein the selected secondary segment is selected based on a selection criteria.

15. The memory device of claim 14 , wherein the selected secondary segment within the primary segment for storing the data word in the dynamic redundancy register is selected based on a counter value of the selected secondary segment.

16. The memory device of claim 15 , wherein each secondary segment of the dynamic redundancy register is associated with two respective counters to track a number of valid entries corresponding to write 1 errors and a number of valid entries corresponding to write 0 errors stored therewithin.

17. The memory device of claim 15 , wherein a direct mapping between the plurality of primary segments of the dynamic redundancy register and the plurality of segments of the memory bank comprise a logical mapping.

18. The memory device of claim 15 , wherein a direct mapping between the plurality of primary segments of the dynamic redundancy register and the plurality of segments of the memory bank comprise a physical mapping.

19. The memory device of claim 14 , wherein the memory bank comprises a plurality of magnetic random access memory (MRAM) cells.

20. The memory device of claim 14 , wherein power cons

Assignees

• Spin Memory Inc

Inventors

• Berger Neal
• Karmakar Susmita
• Pyon Taejin
• Kim Kuk-Hwan

Classifications

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/00

  Package configurations · CPC title

• G11C7/20

  Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory · CPC title

• G11C2207/2245

  Memory devices with an internal cache buffer · CPC title

• G11C11/1675 Primary

  Writing or programming circuits or methods · CPC title