Heuristics for selecting subsegments for entry in and entry out operations in an error cache system with coarse and fine grain segments

Patent metadata

Field	Value
Publication number	US-11119910-B2
Application number	US-201916598634-A
Country	US
Kind code	B2
Filing date	Oct 10, 2019
Priority date	Sep 27, 2016
Publication date	Sep 14, 2021
Grant date	Sep 14, 2021

Abstract

A memory device comprises a memory bank comprising a plurality of addressable memory cells, wherein the memory bank is divided into a plurality of segments. Further, the device comprises a cache memory operable for storing a second plurality of data words, wherein each data word of the second plurality of data words is either awaiting write verification associated with the memory bank or is to be re-written into the memory bank. The cache memory is divided into a plurality of primary segments, wherein each primary segment of the cache memory is direct mapped to a corresponding segment of the plurality of segments, wherein each primary segment is sub-divided into a plurality of secondary segments, and wherein each of the plurality of secondary segments comprises at least one counter for tracking a number of entries stored therein.

First claim

We claim:

1. A memory device comprising:
a memory bank comprising a plurality of addressable memory cells, wherein the memory bank is divided into a plurality of segments;
a pipeline configured to process write operations of a first plurality of data words addressed to the memory bank;
a cache memory operable for storing a second plurality of data words and associated memory addresses, wherein the second plurality of data words are a subset of the first plurality of data words, wherein the cache memory is associated with the memory bank and wherein further each data word of the second plurality of data words is either awaiting write verification associated with the memory bank or is to be re-written into the memory bank, wherein the cache memory is divided into a plurality of primary segments, wherein each primary segment of the cache memory is direct mapped to a corresponding segment of the plurality of segments of the memory bank, wherein each primary segment of the plurality of primary segments of the cache memory is sub-divided into a plurality of secondary segments, and wherein each of the plurality of secondary segments comprises at least one counter for tracking a number of entries stored therein; and
a logic module operable to:
determine a first primary segment of the plurality of primary segments of the cache memory for performing an access operation; and
select a first secondary segment from the plurality of secondary segments within the first primary segment for performing the access operation, wherein the first secondary segment is selected based on a value of a counter of the selected secondary segment.

2. The memory device of claim 1 , wherein the access operation is an entry-in operation into the first secondary segment, wherein the value of the counter of the first secondary segment is lower than corresponding counter values of other secondary segments within the first primary segment.

3. The memory device of claim 1 , wherein the access operation is an entry-out operation for removing an entry from the first secondary segment, wherein the value of the counter of the first secondary segment is higher than corresponding counter values of other secondary segments within the first primary segment.

4. The memory device of claim 3 , wherein the entry-out operation is incident to a verify operation.

5. The memory device of claim 3 , wherein the entry-out operation is incident to a re-write operation.

6. The memory device of claim 1 , wherein to determine the first primary segment of the plurality of primary segments of the cache memory for performing the access operation, the logic module is further operable to:
determine the first primary segment in the cache memory based on an address of a data word associated with the access operation, wherein the first primary segment directly maps to a segment of the memory bank associated with the access operation.

7. The memory device of claim 1 , wherein each of the plurality of secondary segments of the cache memory is associated with two respective counters to keep track of a number of valid entries corresponding to write 1 errors and a number of valid entries corresponding to write 0 errors stored therein.

8. A memory device comprising:
a plurality of memory banks comprising a plurality of addressable memory cells, wherein each of the plurality of memory banks is divided into a plurality of segments;
a pipeline configured to process write operations of a first plurality of data words addressed to the plurality of memory banks;
a cache memory operable for storing a second plurality of data words and associated memory addresses, wherein the second plurality of data words are a subset of the first plurality of data words, wherein the cache memory is associated with the plurality of memory banks and wherein further each data word of the second plurality of data words is either awaiting write verification associated with a memory bank from the plurality of memory banks or is to be re-written into a memory bank from the plurality of memory banks, wherein the cache memory is divided into a plurality of primary segments, wherein each primary segment of the cache memory is direct mapped to a corresponding segment of the plurality of segments of the memory bank, wherein each primary segment of the plurality of primary segments of the cache memory is sub-divided into a plurality of secondary segments, and wherein each of the plurality of secondary segments comprises at least one counter for tracking a number of entries in stored therein; and
a logic module operable to:
determine a first primary segment of the plurality of primary segments of the cache memory for performing an access operation; and
select a first secondary segment from the plurality of secondary segments within the first primary segment for performing the access operation, wherein the first secondary segment is selected based on a value of a counter of the selected secondary segment.

9. The memory device of claim 8 , wherein the access operation is an entry-in operation into the first secondary segment, wherein the value of the counter of the first secondary segment is lower than corresponding counter values of other secondary segments within the first primary segment.

10. The memory device of claim 8 , wherein the access operation is an entry-out operation for removing an entry from the first secondary segment, wherein the value of the counter of the first secondary segment is higher than corresponding counter values of other secondary segments within the first primary segment.

11. The memory device of claim 10 , wherein the entry-out operation is a verify operation.

12. The memory device of claim 10 , wherein the entry-out operation is a re-write operation.

13. The memory device of claim 8 , wherein to determine the primary segment of the plurality of primary segments of the cache memory for performing the access operation, the logic module is further operable to:
determine the first primary segment in the cache memory based on an address of a data word associated with the access operation, wherein the first primary segment directly maps to a segment of the memory bank associated with the access operation.

14. The memory device of claim 8 , wherein each of the plurality of secondary segments of the cache memory is associated with two respective counters to track of a number of valid entries corresponding to write 1 errors and a number of valid entries corresponding to write 0 errors stored therewithin.

15. A memory device comprising:
a memory bank comprising a plurality of addressable memory cells, wherein the memory bank is divided into a plurality of segments;
a pipeline configured to process write operations of a first plurality of data words addressed to the memory bank;
a cache memory operable for storing a second plurality of data words and associated memory addresses, wherein the second plurality of data words are a subset of the first plurality of data words, wherein the cache memory is associated with the memory bank and wherein further each data word of the second plurality of data words is either awaiting write verification associated with the memory bank or is to be re-written into the memory bank, wherein the cache memory is divided into a plurality of primary segments, wherein each primary segment of the cache memory is direct mapped to a corresponding segment of the plurality of segments of the memory bank, wherein each primary segment of the plurality of primary segments of the cache memory is sub-divided into a plurality of secondary segments, and wherein each of the plurality of se

Assignees

• Spin Memory Inc

Inventors

• Berger Neal
• Karmakar Susmita
• Pyon Taejin
• Kim Kuk-Hwan

Classifications

• G11C11/1653

  Address circuits or decoders · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• G06F12/0804

  with main memory updating (G06F12/0806 takes precedence) · CPC title

• G11C29/52

  Protection of memory contents; Detection of errors in memory contents · CPC title

• G06F11/076

  by exceeding a count or rate limit, e.g. word- or bit count limit · CPC title