Instruction level tracing for analyzing processor failure

Patent metadata

Field	Value
Publication number	US-11119890-B2
Application number	US-201916553991-A
Country	US
Kind code	B2
Filing date	Aug 28, 2019
Priority date	Aug 28, 2019
Publication date	Sep 14, 2021
Grant date	Sep 14, 2021

Abstract

A computer-implemented method for instruction-level tracing for analyzing processor failure includes detecting a failure during operation of a processor circuit. The method further includes parsing a miscompare trace to determine a plurality of opcodes executed by the processor prior to the failure. The method further includes generating a workload comprising a set of opcodes by filtering the set of opcodes from the miscompare trace. The method further includes performing a consistency check of the workload to determine a commit ratio of the workload, the commit ratio indicative of a number of times the failure occurs when the workload is executed a predetermined number of times. The method further includes using the workload for debugging the failure based on the commit ratio being above a predetermined threshold.

First claim

What is claimed is:

1. A computer-implemented method for instruction-level tracing for analyzing processor failure to debug a circuit of a processor, the computer-implemented method comprising:
detecting, by the processor, a failure during operation of the processor;
parsing, by the processor, a miscompare trace to determine a plurality of opcodes executed by the processor prior to the failure, the miscompare trace comprising an instruction stream executed by the processor, wherein the instruction stream comprises the opcodes, which indicate machine instructions executed by the processor;
generating, by the processor, a workload comprising a set of opcodes by filtering the set of opcodes from the miscompare trace;
performing, by the processor, a consistency check of the workload to determine a commit ratio of the workload, the commit ratio indicative of a number of times the failure occurs when the workload is executed a predetermined number of times; and
executing, by the processor, the workload for debugging the failure based on the commit ratio being above a predetermined threshold.

2. The computer-implemented method of claim 1 , wherein generating the workload comprises determining a type of the failure and filtering the set of opcodes based on the type of the failure.

3. The computer-implemented method of claim 2 , wherein, based on the type of the failure being core/thread hang, filtering the set of opcodes comprises searching for the last opcode that caused the failure.

4. The computer-implemented method of claim 2 , wherein, based on the type of the failure being one associated with a specific component circuit of the processor, filtering the set of opcodes comprises searching for opcodes that are specifically executed by the specific component circuit.

5. The computer-implemented method of claim 4 , wherein the specific component circuit is one from a group of component circuits comprising a load-store unit, an instruction-fetch unit, and a vector/scalar execution unit.

6. The computer-implemented method of claim 2 , wherein, based on the type of the failure being a CPU/FPU miscompare, filtering the set of opcodes comprises identifying one or more opcodes that are repeated at least a predetermined number of times and including the one or more opcodes in the workload.

7. The computer-implemented method of claim 6 , wherein the method further comprises, optimizing the workload by selecting an optimizing algorithm from a group comprising static optimization, dynamic optimization, and elimination optimization.

8. A system comprising:
a memory; and
a processor coupled with the memory, the processor configured to perform a method for instruction-level tracing for analyzing a processor failure, the method comprising:
detecting a failure during operation of the processor circuit;
parsing a miscompare trace to determine a plurality of opcodes executed by the processor prior to the failure, the miscompare trace comprising an instruction stream executed by the processor, wherein the instruction stream comprises the opcodes, which indicate machine instructions executed by the processor;
generating a workload comprising a set of opcodes by filtering the set of opcodes from the miscompare trace;
performing a consistency check of the workload to determine a commit ratio of the workload, the commit ratio indicative of a number of times the failure occurs when the workload is executed a predetermined number of times; and
executing the workload for debugging the failure based on the commit ratio being above a predetermined threshold.

9. The system of claim 8 , wherein generating the workload comprises determining a type of the failure and filtering the set of opcodes based on the type of the failure.

10. The system of claim 9 , wherein, based on the type of the failure being core/thread hang, filtering the set of opcodes comprises searching for the last opcode that caused the failure.

11. The system of claim 9 , wherein, based on the type of the failure being one associated with a specific component circuit of the processor, filtering the set of opcodes comprises searching for opcodes that are specifically executed by the specific component circuit.

12. The system of claim 11 , wherein the specific component circuit is one from a group of component circuits comprising a load-store unit, an instruction-fetch unit, and a vector/scalar execution unit.

13. The system of claim 9 , wherein, based on the type of the failure being a CPU/FPU miscompare, filtering the set of opcodes comprises identifying one or more opcodes that are repeated at least a predetermined number of times and including the one or more opcodes in the workload.

14. The system of claim 13 , wherein the method further comprises, optimizing the workload by selecting an optimizing algorithm from a group comprising static optimization, dynamic optimization, and elimination optimization.

15. A computer program product comprising a computer-readable storage medium having program instructions embodied therewith, the program instructions executable by a processing circuit to perform a method for instruction-level tracing for analyzing a processor failure, the method comprising:
detecting a failure during operation of a processor circuit;
parsing a miscompare trace to determine a plurality of opcodes executed by the processor prior to the failure, the miscompare trace comprising an instruction stream executed by the processor, wherein the instruction stream comprises the opcodes, which indicate machine instructions executed by the processor;
generating a workload comprising a set of opcodes by filtering the set of opcodes from the miscompare trace;
performing a consistency check of the workload to determine a commit ratio of the workload, the commit ratio indicative of a number of times the failure occurs when the workload is executed a predetermined number of times; and
executing the workload for debugging the failure based on the commit ratio being above a predetermined threshold.

16. The computer program product of claim 15 , wherein generating the workload comprises determining a type of the failure and filtering the set of opcodes based on the type of the failure.

17. The computer program product of claim 16 , wherein, based on the type of the failure being core/thread hang, filtering the set of opcodes comprises searching for the last opcode that caused the failure.

18. The computer program product of claim 16 , wherein, based on the type of the failure being one associated with a specific component circuit of the processor, filtering the set of opcodes comprises searching for opcodes that are specifically executed by the specific component circuit.

19. The computer program product of claim 16 , wherein, based on the type of the failure being a CPU/FPU miscompare, filtering the set of opcodes comprises identifying one or more opcodes that are repeated at least a predetermined number of times and including the one or more opcodes in the workload.

20. The computer program product of claim 19 , wherein the method further comprises, optimizing the workload by selecting an optimizing algorithm from a group comprising static optimization, dynamic optimization, and elimination optimization.

Assignees

• IBM

Inventors

• Chadha Saurabh
• Lewis Daniel
• Chinnakkonda Vidyapoornachary Diyanesh B

Classifications

• G06F11/3636 Primary

  by tracing the execution of the program · CPC title

• G06F11/0751

  Error or fault detection not based on redundancy (power supply failures G06F1/30; network fault management H04L41/06) · CPC title

• G06F11/0721

  within a central processing unit [CPU] · CPC title

• G06F11/348

  Circuit details, i.e. tracer hardware · CPC title

• G06F11/273

  Tester hardware, i.e. output processing circuits {(G06F11/263 takes precedence)} · CPC title