Signal tracing using on-chip memory for in-system post-fabrication debug

Patent metadata

Field	Value
Publication number	US-9720036-B2
Application number	US-201414461528-A
Country	US
Kind code	B2
Filing date	Aug 18, 2014
Priority date	Aug 18, 2014
Publication date	Aug 1, 2017
Grant date	Aug 1, 2017

Abstract

A post-fabrication debug and on-line error checking framework for 2D- and 3D-ICs with integrated memories is described. A design-for-debug (DfD) architecture can include, for an IC with on-chip memory, a debug module connected to a functional bus of the IC. The debug module receives trace data for an interval, generates compact signatures based on the received data, and compares these signatures to expected signatures. Intervals containing erroneous trace data can be identified by the debug module and stored in on-chip memory. A single iteration of signal tracing for debug testing between automated test equipment and the IC is possible.

First claim

We claim:

1. A system-on-chip (SoC), comprising:
a functional bus for communication of data and control signals;
at least one processor coupled to the functional bus;
a memory coupled to the functional bus; and
a debug module coupled to the functional bus, wherein the debug module receives trace data for each interval of an error checking session; generates a compact signature as a function of the received trace data, compares the compact signature to an expected signature for that interval to identify whether or not the interval contains at least one erroneous trace signal; and if the interval contains the at least one erroneous trace signal, provides the interval of the at least one erroneous trace signal for storing in the memory via the functional bus; and if the interval does not contain the at least one erroneous trace signal, the debug module does not store the interval of trace data in the memory, wherein the debug module comprises:
one or more buffers for temporarily storing the trace data of each interval; and
control circuitry comprising a finite state machine (FSM) that schedules operations for retrieving the expected signatures, comparing the compact signatures to the expected signatures, and writing trace signal data to the memory for intervals that contain the at least one erroneous trace signal;
the control circuitry further comprising a first multiple-input signature register (MISR) and a second MISR, wherein the first MISR and the second MISR alternatingly receive the trace data of the error checking session to generate the compact signature for a current interval and hold the compact signature from a previous interval.

2. The SoC of claim 1 , wherein the memory comprises at least one stack of wide I/O dynamic random access memory (DRAM).

3. The SoC of claim 1 , wherein the memory comprises embedded DRAM.

4. The SoC of claim 1 , wherein the one or more buffers comprise:
a trace buffer to initially store the trace data received by the debug module; and
a shadow buffer to receive a copy of the trace data stored in the trace buffer for the interval containing the at least one erroneous trace signal.

5. The SoC of claim 1 , wherein the trace signal data comprises a time stamp and the trace data for the interval having the at least one erroneous trace signal.

6. The SoC of claim 5 , wherein the FSM further schedules operations for packetizing the time stamp and the trace data before writing the trace signal data to the memory.

7. A debug module for an integrated circuit (IC) having on-chip memory, the debug module comprising:
one or more buffers for temporarily storing trace data of each interval of an error checking session; and
control circuitry comprising a finite state machine (FSM) that schedules operations for retrieving a corresponding expected signature for each interval of the error checking session from an on-chip memory, comparing compact signatures of each interval to the corresponding expected signature for that interval, and writing trace signal data to the on-chip memory for intervals that contain the at least one erroneous trace signal, wherein the intervals not containing an erroneous trace signal are not written to the on-chip memory, wherein the control circuitry further comprises a first multiple-input signature register (MISR) and a second MISR,
wherein the first MISR and the second MISR alternatingly receive the trace data of the error checking session to generate the compact signature for a current interval and hold the compact signature from a previous interval,
wherein the compact signature for the current interval is compared to the corresponding expected signature for that interval under the control of the FSM.

8. The debug module of claim 7 , wherein the trace signal data comprises a time stamp and the trace signals for the interval having the at least one erroneous trace signal,
wherein the trace signals for the interval having the at least one erroneous trace signal are written to the on-chip memory from at least one of the one or more buffers under the control of the FSM.

9. The debug module of claim 7 , wherein the one or more buffers comprise:
a trace buffer to initially store the trace data of each interval of the error checking session; and
a shadow buffer to receive a copy of the trace data stored in the trace buffer for the intervals containing the at least one erroneous trace signal.

10. The debug module of claim 9 , wherein the trace signal data comprises a time stamp and the trace data for the interval having the at least one erroneous trace signal,
wherein the trace data for the interval having the at least one erroneous trace signal are written to the on-chip memory from the shadow buffer under the control of the FSM.

11. The debug module of claim 9 , wherein the shadow buffer has an output data bit-width different than that of the trace buffer.

12. The debug module of claim 7 , wherein the error checking session is a debug session.

13. The debug module of claim 7 , wherein the error checking session is a functional program on-line error checking session.

Assignees

• Univ Duke

Inventors

• Deutsch Sergej
• Chakrabarty Krishnendu

Classifications

• G01R31/31705 Primary

  Debugging aspects, e.g. using test circuits for debugging, using dedicated debugging test circuits (generation of test sequences therefor G01R31/31835, using scan test therefor G01R31/318544) · CPC title

• G01R31/31703 Primary

  Comparison aspects, e.g. signature analysis, comparators (concerning scan tests G01R31/318566; concerning testers G01R31/3193) · CPC title

• G06F11/3636

  by tracing the execution of the program · CPC title

• G06F11/348

  Circuit details, i.e. tracer hardware · CPC title