Multi-addend adder circuit for stochastic computing

Patent metadata

Field	Value
Publication number	US-11119732-B2
Application number	US-202017004893-A
Country	US
Kind code	B2
Filing date	Aug 27, 2020
Priority date	Mar 15, 2018
Publication date	Sep 14, 2021
Grant date	Sep 14, 2021

Abstract

A multi-addend adder circuit used for multi-addend addition in a polar representation in stochastic computing. The multi-addend adder circuit includes a buffer circuit and a computing circuit, where the buffer circuit is configured to store to-be-buffered data for at least one cycle and output buffer data, and the computing circuit is configured to process a plurality of pieces of bitstream data and the buffer data and output one piece of bitstream data and the to-be-buffered data, where the piece of output bitstream data is a quotient of dividing a sum of summation data and the buffer data by a scale-down coefficient, the output to-be-buffered data is a remainder of dividing a sum of all summation data until a current cycle by the scale-down coefficient, and the summation data is a quantity of bits whose values are 1 in the plurality of pieces of first bitstream data.

First claim

What is claimed is:

1. A multi-addend adder circuit, comprising:
a computing circuit;
a buffer circuit, configured to: store buffer input data for at least one cycle, and input the buffer input data as buffer output data to the computing circuit; and
the computing circuit, configured to: perform computing on a plurality of pieces of first bitstream data and the buffer output data that are input to the computing circuit, and output second bitstream data and the buffer input data, wherein
the buffer input data is a remainder of dividing a sum of summation data in all cycles until a current cycle by a scale-down coefficient, the summation data in each cycle is a quantity of pieces of first bitstream data whose values are 1 in the plurality of pieces of first bitstream data in the cycle, the second bitstream data is a quotient of dividing a sum of the summation data in each cycle and the buffer output data in each cycle by the scale-down coefficient, the plurality of pieces of first bitstream data and the second bitstream data are data in a polar representation, the scale-down coefficient is a preset parameter, and the cycle is one in which the plurality of pieces of first bitstream data are input.

2. The multi-addend adder circuit of claim 1 , wherein the computing circuit comprises:
a summation circuit configured to receive the plurality of pieces of first bitstream data and generate first intermediate data, and the first intermediate data is the summation data.

3. The multi-addend adder circuit of claim 2 , wherein the computing circuit further comprises:
an adder circuit configured to receive the first intermediate data generated by the summation circuit and the buffer output data generated by the buffer circuit and generate second intermediate data, and the second intermediate data is a sum of the first intermediate data and the buffer output data.

4. The multi-addend adder circuit of claim 3 , wherein the computing circuit further comprises:
a comparator circuit, configured to: receive the second intermediate data generated by the adder circuit, compare the second intermediate data with the scale-down coefficient, and generate the second bitstream data, wherein
when the second intermediate data is greater than or equal to the scale-down coefficient, the second bitstream data is 1; and
when the second intermediate data is less than the scale-down coefficient, the second bitstream data is 0.

5. The multi-addend adder circuit of claim 4 , wherein when the scale-down coefficient is 2 to the power of an integer, the second bitstream data generated by the comparator circuit is a most significant bit of the second intermediate data, wherein the second intermediate data is binary data.

6. The multi-addend adder circuit of claim 2 , wherein the summation circuit is a parallel counter.

7. The multi-addend adder circuit of claim 1 , wherein the computing circuit further comprises:
a subtractor circuit configured to receive the second intermediate data generated by the adder circuit and the second bitstream data generated by the comparator circuit and generate the buffer input data, wherein
when the second bitstream data is 1, the buffer input data is a difference between the second intermediate data and the scale-down coefficient; and
when the second bitstream data is 0, the buffer input data is equal to the second intermediate data.

8. The multi-addend adder circuit of claim 7 , wherein when the scale-down coefficient is 2 to the power of an integer, buffer input data that is in the current cycle and that is generated by the subtractor circuit is a second most significant bit to a least significant bit of the second intermediate data, wherein the second intermediate data is binary data.

9. The multi-addend adder circuit of claim 1 , wherein a quantity of bits of a capacity of the buffer circuit is at least a logarithm of the scale-down coefficient to base 2.

10. A multi-addend adder circuit, comprising:
a summation circuit, wherein a plurality of input ends of the summation circuit are respectively configured to receive a plurality of pieces of first bitstream data;
an adder circuit, wherein a first input end of the adder circuit is coupled to an output end of the summation circuit, and a second input end of the adder circuit is coupled to an output end of a buffer circuit;
a comparator circuit, wherein an input end of the comparator circuit is coupled to an output end of the adder circuit, and an output end of the comparator circuit is configured to output a adding result of the plurality of pieces of first bitstream data;
a subtractor circuit, wherein a first input end of the subtractor circuit is coupled to the output end of the adder circuit, a second input end of the subtractor circuit is coupled to the output end of the comparator, and a output end of the subtractor circuit is coupled to the input end of the buffer circuit.

11. The multi-addend adder circuit of claim 10 , wherein the multi-addend adder circuit further comprises:
the buffer circuit, wherein the input end of the buffer circuit is coupled to the output end of the subtractor circuit, and the output end of the buffer circuit is coupled to the input end of the adder circuit.

12. The multi-addend adder circuit of claim 10 , wherein
the summation circuit is configured to: receive the plurality of pieces of first bitstream data, calculate a quantity of pieces of first bitstream data whose values are 1 in the plurality of pieces of first bitstream data in each cycle, and generate first intermediate data;
the adder circuit is configured to: add the first intermediate data and third intermediate data and generates second intermediate data, wherein the third intermediate data is an output of the subtractor circuit;
the comparator circuit is configured to: receive the second intermediate data and generating second bitstream data, wherein
when the second intermediate data is greater than or equal to a scale-down coefficient, the second bitstream data is 1; and
when the second intermediate data is less than the scale-down coefficient, the second bitstream data is 0, the plurality of pieces of first bitstream data and the second bitstream data are data in a polar representation, and the scale-down coefficient is a preset parameter;

the subtractor circuit is configured to: receive the second intermediate data and the second bitstream data and generate the third intermediate data, wherein
when the second bitstream data is 1, the third intermediate data is a difference between the second intermediate data and the scale-down coefficient; and
when the second bitstream data is 0, the third intermediate data is the second intermediate data; and

the buffer circuit is configured to store buffer data for at least one cycle and output the buffer data; and the cycle is one in which the plurality of pieces of first bitstream data are input.

13. The multi-addend adder circuit of claim 12 , wherein when the scale-down coefficient is 2 to the power of an integer, the second bitstream data generated by the comparator circuit is a most significant bit of the second intermediate data, wherein the second intermediate data is binary data.

14. The multi-addend adder circuit of claim 12 , wherein when the scale-down coefficient is 2 to the power of the integer, the third intermediate data generated by the subtractor circuit is a second most significant bit to a least significant bit of the second intermediate data, wherein the second intermediate data is binary data.

15. The multi-addend adder circuit of claim 10 , wherein the multi-addend adder circuit further

Assignees

• Huawei Tech Co Ltd

Inventors

• Zhang Jian
• Tang Yangyang

Classifications

• G06F7/505 Primary

  in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination · CPC title

• G06F7/02

  Comparing digital values (G06F7/06, {G06F7/22,} G06F7/38 take precedence) · CPC title

• H03K19/21 Primary

  EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical · CPC title

• G06F7/70

  using stochastic pulse trains, i.e. randomly occurring pulses the average pulse rates of which represent numbers {(conversion of analogue signals into stochastic pulse trains and vice versa H03M1/04)} · CPC title

• G06F7/535

  Dividing only · CPC title