LCD panel and EOA module thereof

Patent metadata

Field	Value
Publication number	US-11119377-B2
Application number	US-201716766964-A
Country	US
Kind code	B2
Filing date	Dec 1, 2017
Priority date	Dec 1, 2017
Publication date	Sep 14, 2021
Grant date	Sep 14, 2021

Abstract

A liquid crystal display (LCD) panel and an emission D-IC on array (EOA) module (10′) thereof are provided. The EOA module includes a high-level generating unit, a resetting unit, and a restoring unit. The high-level generating unit is configured to generate an output signal, where the output signal is at high level when a first clock signal (CLK) is at high level. The resetting unit is configured to reset the output signal from high level to low level when a second clock signal (CLKB) and a scan signal (Gn) of a current stage are simultaneously at high level. The restoring unit is configured to restore the output signal from low level to high level when a scan signal (Gn+1) of a subsequent stage is at high level.

First claim

What is claimed is:

1. An emission D-IC on array (EOA) module, comprising:
a high-level generating unit configured to generate an output signal according to a first clock signal, the output signal being at high level when the first clock signal is at high level;
a resetting unit configured to reset, according to a second clock signal and a scan signal of a current stage, the output signal from high level to low level when the second clock signal and the scan signal of the current stage are simultaneously at high level, the second clock signal having a frequency twice a frequency of the first clock signal; and
a restoring unit configured to restore, according to a scan signal of a subsequent stage, the output signal from low level to high level when the scan signal of the subsequent stage is at high level.

2. The EOA module of claim 1 , wherein the high-level generating unit comprises a first N-type thin film transistor (TFT) T 11 , a second N-type TFT T 12 , and a capacitor C, wherein a gate and a drain of the first TFT T 11 are both coupled with a transmission line for transmitting the first clock signal, and a source of the first TFT T 11 is coupled with a gate of the second TFT T 12 , wherein a drain of the second TFT T 12 is coupled with a transmission line for transmitting a first high-level signal, and a source of the second TFT T 12 is an output of the EOA module, and wherein the capacitor is coupled between the gate of the second TFT T 12 and the source of the second TFT T 12 .

3. The EOA module of claim 2 , wherein the high-level generating unit further comprises a third N-type TFT T 13 , wherein a drain of the third TFT T 13 is coupled with a transmission line for transmitting a second high-level signal, a gate of the third TFT T 13 is coupled with the source of the second TFT T 12 , and a source of the third TFT T 13 is coupled with the gate of the second TFT T 12 .

4. The EOA module of claim 3 , wherein the resetting unit comprises a fourth N-type TFT T 14 , a fifth N-type TFT T 15 , and a sixth N-type TFT T 16 , wherein a gate of the fourth TFT T 14 is coupled with a transmission line for transmitting the scan signal of the current stage, a drain of the fourth TFT T 14 is coupled with a transmission line for transmitting the second clock signal, and a source of the fourth TFT T 14 is coupled with a gate of the fifth TFT T 15 and a gate of the sixth TFT T 16 , wherein a source of the fifth TFT T 15 and a source of the sixth TFT T 16 are coupled with a transmission line for transmitting a low-level signal, a drain of the fifth TFT T 15 is coupled with the source of the second TFT T 12 , and a drain of the sixth TFT T 16 is coupled with the source of the first TFT T 11 .

5. The EOA module of claim 4 , wherein the restoring unit comprises a seventh N-type TFT T 17 , wherein a gate of the seventh TFT T 17 is coupled with a transmission line for transmitting the scan signal of the subsequent stage, a drain of the seventh TFT T 17 is coupled with the source of the fourth TFT T 14 , and a source of the seventh TFT T 17 is coupled with the transmission line for transmitting the low-level signal.

6. The EOA module of claim 5 , wherein the first TFT T 11 , the second TFT T 12 , and the third TFT T 13 are switched on when the first clock signal is at high level.

7. The EOA module of claim 6 , wherein the fourth TFT T 14 , the fifth TFT T 15 , and the sixth TFT T 16 are switched on when the second clock signal is at high level.

8. The EOA module of claim 7 , wherein the second TFT T 12 is switched off after the sixth TFT T 16 is switched on.

9. A liquid crystal display panel, comprising:
an emission D-IC on array (EOA) module disposed in a boundary area of the liquid crystal display panel and comprising:
a high-level generating unit configured to generate an output signal according to a first clock signal, the output signal being at high level when the first clock signal is at high level;
a resetting unit configured to reset, according to a second clock signal and a scan signal of a current stage, the output signal from high level to low level when the second clock signal and the scan signal of the current stage are simultaneously at high level, the second clock signal having a frequency twice a frequency of the first clock signal; and
a restoring unit configured to restore, according to a scan signal of a subsequent stage, the output signal from low level to high level when the scan signal of the subsequent stage is at high level.

10. The liquid crystal display panel of claim 9 , wherein the high-level generating unit comprises a first N-type thin film transistor (TFT) T 11 , a second N-type TFT T 12 , and a capacitor C, wherein a gate and a drain of the first TFT T 11 are both coupled with a transmission line for transmitting the first clock signal, and a source of the first TFT T 11 is coupled with a gate of the second TFT T 12 , wherein a drain of the second TFT T 12 is coupled with a transmission line for transmitting a first high-level signal, and a source of the second TFT T 12 is an output of the EOA module, and wherein the capacitor is coupled between the gate of the second TFT T 12 and the source of the second TFT T 12 .

11. The liquid crystal display panel of claim 10 , wherein the high-level generating unit further comprises a third N-type TFT T 13 , wherein a drain of the third TFT T 13 is coupled with a transmission line for transmitting a second high-level signal, a gate of the third TFT T 13 is coupled with the source of the second TFT T 12 , and a source of the third TFT T 13 is coupled with the gate of the second TFT T 12 .

12. The liquid crystal display panel of claim 11 , wherein the resetting unit comprises a fourth N-type TFT T 14 , a fifth N-type TFT T 15 , and a sixth N-type TFT T 16 , wherein a gate of the fourth TFT T 14 is coupled with a transmission line for transmitting the scan signal of the current stage, a drain of the fourth TFT T 14 is coupled with a transmission line for transmitting the second clock signal, and a source of the fourth TFT T 14 is coupled with a gate of the fifth TFT T 15 and a gate of the sixth TFT T 16 , wherein a source of the fifth TFT T 15 and a source of the sixth TFT T 16 are coupled with a transmission line for transmitting a low-level signal, a drain of the fifth TFT T 15 is coupled with the source of the second TFT T 12 , and a drain of the sixth TFT T 16 is coupled with the source of the first TFT T 11 .

13. The liquid crystal display panel of claim 12 , wherein the restoring unit comprises a seventh N-type TFT T 17 , wherein a gate of the seventh TFT T 17 is coupled with a transmission line for transmitting the scan signal of the subsequent stage, a drain of the seventh TFT T 17 is coupled with the source of the fourth TFT T 14 , and a source of the seventh TFT T 17 is coupled with the transmission line for transmitting the low-level signal.

14. The liquid crystal display panel of claim 13 , wherein the first TFT T 11 , the second TFT T 12 , and the third TFT T 13 are switched on when the first clock signal is at high level.

15. The liquid crystal display panel of claim 14 , wherein the fourth TFT T 14 , the fifth TFT T 15 , and the sixth TFT T 16 are switched on when the second clock signal is at high level.

16. The liquid crystal display panel of claim 15 , wherein the second TFT T 12 is switched off after the sixth TFT T 16 is switched on.

17. The liquid crystal display panel of claim 16 , further comprising a gate D-IC on array (GOA) module, wherein the EOA module is electrically

Assignees

• Shenzhen Royole Technologies Co Ltd

Inventors

• Kim Ji Ha
• XIONG Nana
• Chen Dan

Classifications

• H10D86/60

  wherein the TFTs are in active matrices · CPC title

• H10D86/40

  characterised by multiple TFTs · CPC title

• G09G2320/0223

  Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title