Display panel

Patent metadata

Field	Value
Publication number	US-2016335974-A1
Application number	US-201615219288-A
Country	US
Kind code	A1
Filing date	Jul 26, 2016
Priority date	Apr 26, 2013
Publication date	Nov 17, 2016
Grant date	—

Abstract

A display panel includes a substrate, a plurality of pixels, a plurality of scan lines, a pull-down control circuit, and a gate driving circuit. The pixels are disposed on a display area of the substrate. The scan lines are disposed on the substrate and respectively coupled to the corresponding pixels. The pull-down control circuit is disposed on a peripheral area of the substrate, receives a plurality of clock signals, and has a plurality of pull-down units to provide a plurality of pull-down signals. The gate driving circuit is disposed on the peripheral area and has a plurality of shift registers. The shift registers are coupled to the scan lines to provide a plurality of gate driving signals and pull down the gate driving signals in sequence according to the pull-down signals. The pull-down control circuit and the gate driving circuit are arranged along a side of the display area.

First claim

What is claimed is:

1 . A display panel, comprising:
a substrate, having a display area and a peripheral area; a plurality of pixels, disposed on the display area; a plurality of scan lines, disposed on the substrate and respectively coupled to the corresponding pixels, the scan lines extending from the display area to the peripheral area; a pull-down control circuit, disposed on the peripheral area, the pull-down control circuit receiving a plurality of clock signals and having a plurality of pull-down units to provide a plurality of first pull-down signals; a push-up control circuit, disposed on the peripheral area, the push-up control circuit receiving the clock signals, the push-up control circuit having a plurality of push-up units to provide a plurality of push-up signals; and a gate driving circuit, disposed on the peripheral area and having a plurality of shift registers, wherein the shift registers are coupled to the scan lines to provide a plurality of gate driving signals, the shift registers are coupled to the pull-down control circuit to receive the first pull-down signals, the shift registers are coupled to the push-up control circuit to receive the push-up signals, each of the shift registers receives the corresponding push-up signal respectively to enable the corresponding gate driving signal, the shift registers enable the gate driving signals in sequence according to the clock signals, and the shift registers pull down the gate driving signals in sequence according to the first pull-down signals, respectively, wherein the pull-down control circuit and the gate driving circuit are arranged along a side of the display area, and the push-up control circuit and the gate driving circuit are arranged along the side of the display area, wherein each of the shift registers comprises: a pre-charge unit for pre-charging an internal voltage; a voltage push-up unit, coupled to the pre-charge unit for pushing up i th gate driving signal of the gate driving signals according to the internal voltage, wherein i is an positive integer; and a voltage pull-down unit, receiving the corresponding first pull-down signal for pulling down the internal voltage and the i th gate driving signal according to the corresponding first pull-down signal.

2 . The display panel as claimed in claim 1 , wherein enabling periods of the clock signals partially overlap and are different from one another.

3 . The display panel as claimed in claim 1 , wherein the pre-charge unit comprises:
a first transistor, wherein a first terminal of the first transistor receives a forward scanning voltage, a second terminal of the first transistor is coupled to the internal voltage, and a control terminal of the first transistor receives (i−1) th gate driving signal of the gate driving signals or a start signal; and a second transistor, wherein a first terminal of the second transistor receives a reverse scanning voltage, a second terminal of the second transistor is coupled to the internal voltage, and a control terminal of the second transistor receives (i+1) th gate driving signal of the gate driving signals.

4 . The display panel as claimed in claim 1 , wherein the voltage pull-down unit comprises:
a third transistor, wherein a first terminal of the third transistor is coupled to the internal voltage, a second terminal of the third transistor receives a gate low voltage, and a control terminal of the third transistor receives the corresponding first pull-down signal; and a fourth transistor, wherein a first terminal of the fourth transistor is coupled to the i th gate driving signal, a second terminal of the fourth transistor receives the gate low voltage, and a control terminal of the fourth transistor receives the corresponding first pull-down signal.

5 . The display panel as claimed in claim 1 , wherein the pre-charge unit comprises:
a fifth transistor, wherein a first terminal and a control terminal of the fifth transistor receive (i−1) th gate driving signal of the gate driving signals, and a second terminal of the fifth transistor is coupled to the internal voltage.

6 . The display panel as claimed in claim 1 , wherein the pull-down units further provide a plurality of second pull-down signals, and the voltage pull-down unit receives the corresponding second pull-down signal to pull down the i th gate driving signal according to the corresponding first pull-down signal and to pull down the internal voltage according to the corresponding second pull-down signal.

7 . The display panel as claimed in claim 6 , wherein the voltage pull-down unit comprises:
a sixth transistor, wherein a first terminal of the sixth transistor receives the corresponding second pull-down signal, a second terminal of the sixth transistor receives a gate low voltage, and a control terminal of the sixth transistor receives the internal voltage; an seventh transistor, wherein a first terminal of the seventh transistor is coupled to the internal voltage, a second terminal of the seventh transistor receives the gate low voltage, and a control terminal of the seventh transistor receives the corresponding second pull-down signal; and an eighth transistor, wherein a first terminal of the eighth transistor is coupled to the i th gate driving signal, a second terminal of the eighth transistor receives the gate low voltage, and a control terminal of the eighth transistor receives the corresponding first pull-down signal.

8 . The display panel as claimed in claim 6 , wherein each of the pull-down units comprises:
a ninth transistor, wherein a first terminal of the ninth transistor receives a forward scanning voltage, a second terminal of the ninth transistor is coupled to the corresponding first pull-down signal, and a control terminal of the ninth transistor receives a first clock signal of the clock signals; a tenth transistor, wherein a first terminal of the tenth transistor receives a reverse scanning voltage, a second terminal of the tenth transistor is coupled to the corresponding first pull-down signal, and a control terminal of the tenth transistor receives a second clock signal of the clock signals; an eleventh transistor, wherein a first terminal of the eleventh transistor receives the forward scanning voltage, a second terminal of the ninth transistor is coupled to the corresponding second pull-down signal, and a control terminal of the eleventh transistor receives a third clock signal of the clock signals; and a twelfth transistor, wherein a first terminal of the twelfth transistor receives the reverse scanning voltage, a second terminal of the twelfth transistor is coupled to the corresponding second pull-down signal, and a control terminal of the twelfth transistor receives a fourth clock signal of the clock signals, wherein enabling periods of the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal overlap with one another, and according to phase sequence, these clock signals are arranged in an order of the second clock signal, the third clock signal, the first clock signal, and the fourth clock signal.

9 . The display panel as claimed in claim 6 , wherein each of the pull-down units comprises:
a thirteenth transistor, wherein a first terminal and a control terminal of the thirteenth transistor receive a fifth clock signal of the clock signals, and a second terminal of the thirteenth transistor is coupled to the corresponding first pull-down signal; and a fourteenth transistor, wherein a first terminal and a control terminal of the fourteenth transistor receive a sixth clock signal of the clock signals, and a second terminal of the fourteenth transistor is coupled to the corresponding second pu

Assignees

• Chunghwa Picture Tubes Ltd

Inventors

• Li Wei-Lung
• Lai Chih-Wen

Classifications

• G09G3/3677 Primary

  suitable for active matrices only · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title

• G11C19/28

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title