Method for producing a printed circuit board having thermal through-contacts

Patent metadata

Field	Value
Publication number	US-11116071-B2
Application number	US-201816754693-A
Country	US
Kind code	B2
Filing date	Oct 8, 2018
Priority date	Oct 12, 2017
Publication date	Sep 7, 2021
Grant date	Sep 7, 2021

Abstract

In a printed circuit board (1), thermal vias (19) are formed between the lower surface (A) and an upper surface (B) of the substrate plate (10) of the printed circuit board through the steps of: applying a respective solder resist mask (21, 31) to the lower surface (A) and the upper surface (B); applying solder to the lower surface (A) and reflow soldering the solder, wherein the solder penetrates into the boreholes (20) and forms convex menisci (26) protruding beyond the edge (22) of the respective boreholes on the lower surface (A); and creating regions (35) on the upper surface (B), which are freed from solder resist material, and which are intended for contacting at least one electronic component (17) on the upper surface and each of which comprise at least one of the thermal vias. Subsequently, the upper surface (B) can be provided with electrical components (17) on these regions (35). The first solder resist mask (21) has a respective region (23) that is free of solder resist on the lower surface around the edge of every borehole (20).

First claim

The invention claimed is:

1. A method for producing thermal vias ( 19 ) in a printed circuit board, proceeding from a substrate plate ( 101 ) with a plurality of boreholes ( 11 , 12 , 13 , 14 ) preformed therein, which are formed between a lower surface (A) and an upper surface (B) of the substrate plate ( 101 ) and are located at positions where thermal vias are to be produced respectively, the method comprising the following steps:
applying a first and a second solder resist mask ( 21 , 31 ) onto the lower surface (A) and the upper surface (B) respectively, wherein the first solder resist mask ( 21 ) has, at the preformed boreholes ( 11 - 14 ), respective regions ( 23 ) free from solder resist around the edges ( 22 ) of each bore on the lower surface, and wherein the second solder resist mask ( 31 ) extends to at least the edges ( 32 ) of the boreholes on the upper surface for at least a majority of the preformed boreholes ( 11 - 14 );
applying solder ( 16 ) onto the lower surface (A) and reflow soldering of the solder, wherein the solder penetrates into the bores ( 11 - 14 ) and forms on the lower surface (A) convex menisci ( 26 ) protruding beyond the edge ( 22 ) of the respective boreholes; and then
clearing regions ( 35 ) on the upper surface (B), which regions are predetermined for the contacting of at least one electronic component ( 18 ) on the upper surface and respectively comprise at least one of the thermal vias, by removal of the second solder resist mask ( 31 ) at least in said regions on the upper surface.

2. The method according to claim 1 , wherein in the first solder resist mask ( 21 ) the regions ( 23 ) free from solder resist on the lower surface are configured to be circular ring-shaped.

3. The method according to claim 2 , wherein the solder resist-free regions ( 23 ) of immediately adjacent boreholes touch one another, whereby between the free regions, areas ( 25 ) with solder resist are formed.

4. The method of claim 3 , wherein the areas ( 25 ) with solder resist have the shape of quadrilaterals or triangles delimited by concave curve segments.

5. The method according to claim 1 , wherein the second solder resist mask ( 31 ) in at least a part of said boreholes extends over the edge ( 32 ), forming a freestanding inwardly projecting ring ( 34 ) there, respectively.

6. The method according to claim 1 , wherein the second solder resist mask ( 31 ) in at least a portion of said boreholes extends to the edge ( 32 ), wherein in these boreholes the edge ( 33 ) of the second solder resist mask is flush with the edge ( 32 ) of the borehole.

7. The method according to claim 1 , wherein the substrate plate is held with the lower surface (A) oriented upwards during the step of the applying of solder.

8. The method according to claim 1 , further comprising a subsequent additional step:
equipping the upper surface (B) with at least one electronic component ( 18 ) on the cleared regions ( 35 ) for contacting.

9. The method according to claim 1 , wherein the menisci ( 26 ) produced during the reflow soldering of the solder on the lower surface (A) form convex calottes respectively over the boreholes.

10. The method according to claim 1 , further comprising an additional step, carried out in advance:
lining of the preformed boreholes ( 11 - 14 ) with a metal.

11. The method of claim 10 , wherein the metal has a high electrical conductivity.

12. The method of claim 11 , wherein the metal is copper.

13. The method of claim 10 , wherein the lining is by a galvanic method.

14. The method according to claim 1 , wherein during the reflow soldering of the solder, the bores ( 11 - 14 ) into which the solder penetrates are filled by the solder ( 16 ).

Assignees

• Zkw Group Gmbh

Inventors

• Edlinger Erik

Classifications

• H05K3/0094

  Filling or covering plated through-holes or blind plated vias, e.g. for masking or for mechanical reinforcement · CPC title

• H05K2203/0455

  PTH for surface mount device [SMD], e.g. wherein solder flows through the PTH during mounting · CPC title

• H05K2201/09563

  Metal filled via · CPC title

• H05K3/42

  Plated through-holes {or plated via connections} · CPC title

• H05K2203/1476

  Same or similar kind of process performed in phases, e.g. coarse patterning followed by fine patterning · CPC title