Interconnect circuit methods and devices

Patent metadata

Field	Value
Publication number	US-11116070-B2
Application number	US-201816034899-A
Country	US
Kind code	B2
Filing date	Jul 13, 2018
Priority date	Jul 13, 2017
Publication date	Sep 7, 2021
Grant date	Sep 7, 2021

Abstract

Provided are interconnect circuits and methods of forming thereof. A method may involve laminating a substrate to a conductive layer followed by patterning the conductive layer. This patterning operation forms individual conductive portions, which may be also referred to as traces or conductive islands. The substrate supports these portions relative to each other during and after patterning. After patterning, an insulator may be laminated to the exposed surface of the patterned conductive layer. At this point, the conductive layer portions are also supported by the insulator, and the substrate may optionally be removed, e.g., together with undesirable portions of the conductive layer. Alternatively, the substrate may be retained as a component of the circuit and the undesirable portions of the patterned conductive layer may be removed separately. These approaches allow using new patterning techniques as well as new materials for substrates and/or insulators.

First claim

What is claimed is:

1. A method of forming an interconnect circuit, the method comprising:
laminating a substrate to a conductive layer,
wherein the conductive layer is a metal foil, comprising a first side and a second side, opposite of the first side, and having a constant thickness, and
wherein the substrate comprises an adhesive layer, laminated to the second side of the conductive layer;

patterning the conductive layer, while the conductive layer remains laminated to the substrate,
wherein patterning the conductive layer forms a first conductive portion and a second conductive portion of the conductive layer, at least partially separated from the first conductive portion,
wherein the substrate maintains orientation of the first conductive portion relative to the second conductive portion after patterning the conductive layer;

after patterning the conductive layer, laminating a first insulator to the first side of the conductive layer; and
after laminating the first insulator to the first side of the conductive layer, removing the substrate from the conductive layer,
wherein the first insulator maintains the orientation of the first conductive portion relative to the second conductive portion after the substrate is removed.

2. The method of claim 1 , wherein the first insulator comprises an opening prior to laminating the first insulator to the conductive layer.

3. The method of claim 2 , wherein the opening at least partially overlaps with the first conductive portion of the conductive layer such that the first side of the first conductive portion remains at least partially exposed after laminating to the first insulator.

4. The method of claim 3 , wherein a portion of the first insulator forming the opening is laminated to the first side of the first conductive portion.

5. The method of claim 1 ,
wherein patterning the conductive layer further forms a third portion of the conductive layer positioned between the first conductive portion and the second conductive portion of the conductive layer, and
wherein the method further comprises removing the third portion of the conductive layer from the substrate prior to laminating the first insulator to the first side of the conductive layer.

6. The method of claim 1 ,
wherein patterning the conductive layer further forms a third portion of the conductive layer positioned between the first conductive portion and the second conductive portion of the conductive layer, and
wherein the method further comprises removing the third portion of the conductive layer after laminating the first insulator to the first side of the conductive layer.

7. The method of claim 6 , wherein the third portion of the conductive layer is removed while removing the substrate from the conductive layer.

8. The method of claim 6 , wherein the third portion of the conductive layer is removed after removing the substrate from the conductive layer.

9. The method of claim 6 , wherein the third portion is connected to each of the first conductive portion and the second conductive portion and operable to support the first conductive portion and the second conductive portion.

10. The method of claim 1 , wherein patterning the conductive layer completely removes a portion of the conductive layer positioned between the first conductive portion and the second conductive portion.

11. The method of claim 1 , wherein patterning the conductive layer forms one or more pattern openings in the conductive layer, wherein the one or more pattern openings are disposed between the between the first conductive portion and the second conductive portion of the conductive layer.

12. The method of claim 11 , wherein each of the one or more pattern openings comprises tapered side walls.

13. The method of claim 11 , wherein each of the one or more pattern openings comprises substantially parallel side walls.

14. The method of claim 13 , wherein the substantially parallel side walls protrude above a portion of the first side of the conductive layer positioned away from the one or more pattern openings.

15. The method of claim 11 , wherein at least one of the one or more pattern openings have a variable width.

16. The method of claim 1 , wherein patterning the conductive layer comprises a process selected from the group consisting of chemical etching, electrochemical etching, mechanical cutting, laser cutting, and laser ablation.

17. The method of claim 1 , wherein removing the substrate further comprises deactivating at least a portion of the adhesive layer.

18. The method of claim 17 , wherein at least the portion of the adhesive layer, deactivated while removing the substrate, overlaps with the first conductive portion and the second conductive portion of the conductive layer.

19. The method of claim 18 , wherein a remaining portion of the adhesive layer, different from at least the portion of the adhesive layer deactivated while removing the substrate, remains activated.

20. The method of claim 19 ,
wherein patterning the conductive layer further forms a third portion of the conductive layer positioned between the first conductive portion and the second conductive portion of the conductive layer,
wherein the remaining portion of the adhesive layer overlaps with the third portion of the conductive layer, and
wherein the method further comprises removing the third portion of the conductive layer while removing the substrate.

Assignees

• Cellink Corp

Inventors

• Coakley Kevin Michael
• Brown Malcolm Parker
• Yang Dongao
• Miller Michael Lawrence
• Lego Paul Henry

Classifications

• H01M50/519

  comprising printed circuit boards [PCB] · CPC title

• H05K3/007 Primary

  Manufacture or processing of a substrate for a printed circuit board supported by a temporary or sacrificial carrier (H05K1/187, H05K3/20 and H05K3/4682 take precedence) · CPC title

• H05K2201/015

  Fluoropolymer, e.g. polytetrafluoroethylene [PTFE] · CPC title

• H05K2201/0154

  Polyimide · CPC title

• H05K3/0073

  Masks not provided for in groups H05K3/02 - H05K3/46, e.g. for photomechanical production of patterned surfaces · CPC title