System and method for adjusting clock-data timing in a multi-lane data communication link

Patent metadata

Field	Value
Publication number	US-11115176-B1
Application number	US-202016809477-A
Country	US
Kind code	B1
Filing date	Mar 4, 2020
Priority date	Mar 4, 2020
Publication date	Sep 7, 2021
Grant date	Sep 7, 2021

Abstract

Clock-data timing in a multi-lane serial data communication link may be adjusted to compensate for drift. A reference lane may be selected and periodically trained to adjust clock-data timing. In response to initiation of a first lane transitioning from an active state to an inactive state, first information representing the clock-data timing of the reference lane at the time that transition is initiated may be determined. Then, in response to initiation of the first lane transitioning back from the inactive state to the active state, second information representing the clock-data timing of the reference lane at the time that transition is initiated may be determined. The clock-data timing of the first lane may be adjusted based on the first information and the second information.

First claim

What is claimed is:

1. A method for adjusting clock-data timing in a multi-lane serial data communication link, comprising:
periodically performing training to adjust clock-data timing of a reference lane, the multi-lane serial data communication link comprising a plurality of lanes including a reference lane and a first lane;
determining first information representing the clock-data timing of the reference lane in response to the first lane transitioning from an active state to an inactive state;
determining second information representing the clock-data timing of the reference lane in response to the first lane transitioning from the inactive state to the active state;
adjusting the clock-data timing of the first lane based on the first information and the second information in response to the first lane transitioning from the inactive state to the active state; and
receiving data on the first lane using the adjusted clock-data timing.

2. The method of claim 1 , wherein the reference lane is in the active state a cumulatively greater amount of time than the first one of the other lanes.

3. The method of claim 1 , wherein the reference lane is in the active state a cumulatively greater amount of time than any of the other lanes.

4. The method of claim 1 , wherein the multi-lane serial data communication link further comprises a plurality of transmit lanes, and the method further comprises transmitting data on the plurality of transmit lanes.

5. The method of claim 1 , wherein the first information and the second information each comprises a phase interpolator setting, and adjusting the clock-data timing comprises adjusting clock signal timing by applying a difference between the first information and the second information to a clock phase interpolator.

6. The method of claim 1 , further comprising:
determining third information representing the clock-data timing of the reference lane in response to a second lane of the other lanes transitioning from an active state to an inactive state;
determining fourth information representing the clock-data timing of the reference lane in response to the second lane transitioning from the inactive state to the active state;
adjusting the clock-data timing of the second lane based on the third information and the fourth information; and
receiving data on the second lane using the adjusted clock-data timing.

7. The method of claim 1 , wherein the multi-lane serial data communication link comprises a serializer-deserializer.

8. The method of claim 1 , wherein the multi-lane serial data communication link is between two integrated circuit chips.

9. The method of claim 1 , wherein multi-lane serial data communication link is included in a system-on-a-chip (SoC).

10. The method of claim 1 , wherein multi-lane serial data communication link is included in one of: a computing system, a portable computing device, an Internet of Things (IoT) device, a virtual reality (VR) system, or an augmented reality (AR) system.

11. An apparatus for adjusting clock-data timing in a multi-lane serial data communication link, comprising:
a plurality of receiver circuits, each receiver circuit configured to receive data on a corresponding lane of a plurality of lanes of the multi-lane serial data communication link based on relative timing between a clock signal and a data signal, the plurality of lanes including a reference lane and a first lane, each receiver circuit providing adjustable clock-data timing for the corresponding lane;
a timing controller system coupled to each of the plurality of receiver circuits, the timing controller system configured to periodically perform training to adjust the clock-data timing for the reference lane, the timing controller system further configured to:
determine first information representing the clock-data timing for the reference lane in response to the first lane transitioning from an active state to an inactive state;
determine second information representing the clock-data timing for the reference lane in response to the first lane transitioning from the inactive state to the active state;
adjust one of the receiver circuits corresponding to the first lane based on the first information and the second information.

12. The apparatus of claim 11 , wherein the reference lane is in the active state a cumulatively greater amount of time than the first one of the other lanes.

13. The apparatus of claim 11 , wherein the reference lane is in the active state a cumulatively greater amount of time than any of the other lanes.

14. The apparatus of claim 11 , further comprising a plurality of transmitter circuits, each transmitter circuit configured to transmit data on a corresponding lane of the plurality of lanes.

15. The apparatus of claim 11 , wherein the timing controller system is further configured to:
determine third information representing the clock-data timing for the reference lane in response to a second lane other than the reference lane and the first lane transitioning from an active state to an inactive state;
determine fourth information representing the clock-data timing for the reference lane in response to the second lane transitioning from the inactive state to the active state;
adjust one of the receiver circuits corresponding to the second lane based on the third information and the fourth information.

16. The apparatus of claim 11 , wherein each receiver circuit includes a clock phase interpolator configured to adjust the clock-data timing for the corresponding lane.

17. The apparatus of claim 11 , wherein each receiver circuit includes a deserializer circuit.

18. The apparatus of claim 11 , wherein the plurality of receiver circuits and the timing controller system are included in a first integrated circuit chip coupled to a second integrated circuit chip via the reference lane and other lanes.

19. The apparatus of claim 11 , wherein multi-lane serial data communication link is included in a system-on-a-chip (SoC).

20. The apparatus of claim 11 , wherein multi-lane serial data communication link is included in one of: a computing system, a portable computing device, an Internet of Things (IoT) device, a virtual reality (VR) system, or an augmented reality (AR) system.

Assignees

• Qualcomm Inc

Inventors

• Goudarzi Hadi
• Chang Chia Heng

Classifications

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• H04L7/10

  Arrangements for initial synchronisation · CPC title

• H04L7/0008

  Synchronisation information channels, e.g. clock distribution lines · CPC title

• H04L7/033

  using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop · CPC title

• G06F1/3253

  Power saving in bus · CPC title