High performance interconnect link state transitions

Patent metadata

Field	Value
Publication number	US-2016179730-A1
Application number	US-201414578175-A
Country	US
Kind code	A1
Filing date	Dec 19, 2014
Priority date	Dec 19, 2014
Publication date	Jun 23, 2016
Grant date	—

Abstract

A supersequence is sent to another device to indicate a transition from a partial width link state to another active link state. The supersequence is to be sent over one or more lanes of a link and is to include at least a portion of a start of data sequence (SDS) to include a predefined sequence and a byte number value. The byte number value is to indicate a number of bytes measured from a preceding control interval.

First claim

What is claimed is:

1 . An apparatus comprising:
protocol logic to send a supersequence to another device to indicate a transition from a partial width link state to another active link state, wherein the supersequence is to be sent over one or more lanes of a link and is to comprise at least a portion of a start of data sequence (SDS) to comprise a predefined sequence and a byte number value, and the byte number value is to indicate a number of bytes measured from a preceding control interval.

2 . The apparatus of claim 1 , wherein the supersequence is further to comprise an electrical ordered set and one or more training sequences.

3 . The apparatus of claim 2 , wherein the supersequence is to end with the SDS.

4 . The apparatus of claim 2 , wherein the electrical ordered set is to be used to condition the lane, the one or more training sequences are to facilitate byte lock and deskewing of the lanes, and the SDS is to align with a clean flit boundary.

5 . The apparatus of claim 1 , wherein the predefined sequence is to comprise a first portion to comprise a first set of bytes each with a first value, and a second portion to comprise a second set of bytes each with a different second value.

6 . The apparatus of claim 5 , wherein the first value is hexadecimal value 0xE1 and the second value is hexadecimal value 0xAA.

7 . The apparatus of claim 6 , wherein the SDS comprises at least 16 bytes, the first portion comprises a single first byte of the SDS, the second portion comprises the next twelve bytes of the SDS, and the byte number value occupies the final three bytes of the SDS.

8 . The apparatus of claim 1 , wherein the byte number value comprises an ordinal number value of the number of bytes and further comprises a bit-wise compliment of the ordinal number.

9 . The apparatus of claim 1 , wherein the other active link state comprises a link state with more active lanes than the partial width state.

10 . The apparatus of claim 1 , further comprising:
a state manager to enter the other active state, wherein the other active state activates at least one additional lane of the link; and a transmitter to send data on active lanes in the other active state.

11 . The apparatus of claim 1 , wherein the start of data sequence comprises a partial start of data sequence (SDSp).

12 . An apparatus comprising:
a receiver to receive a supersequence from another device, wherein the supersequence is defined to indicate a transition from a partial width link state to another active link state, the supersequence is to be sent over one or more lanes of a link and is to comprise a start of data sequence (SDS) to comprise a predefined sequence and a byte number value, and the byte number value is to indicate a number of bytes measured from a preceding control interval.

13 . The apparatus of claim 12 , wherein the control interval is a particular one of a series of control interval embedded in a link layer data stream.

14 . The apparatus of claim 13 , wherein physical layer control messages are to be sent in at least some of the control intervals and the control intervals interrupt the link layer data stream.

15 . The apparatus of claim 12 , further comprising a state manager to enter the other active link state based on the supersequence.

16 . The apparatus of claim 12 , wherein the supersequence is further to comprise an electrical ordered set and one or more training sequences.

17 . The apparatus of claim 16 , wherein at least one of the training sequences comprises a fast training sequence.

18 . The apparatus of claim 17 , wherein the fast training sequence is unscrambled.

19 . The apparatus of claim 17 , wherein the training sequences comprises a plurality of fast training sequences and one of the fast training sequences comprises a partial fast training sequence.

20 . The apparatus of claim 19 , wherein the partial fast training sequence is to be truncated such that the SDS ends on a clean flit boundary.

21 . A computer readable medium comprising code that, when executed, is to cause a computing device to:
send a supersequence from another device, wherein the supersequence is defined to indicate a transition from a partial width link state to another active link state, the supersequence is to be sent over one or more lanes of a link and is to comprise a start of data sequence (SDS) to comprise a predefined sequence and a byte number value, and the byte number value is to indicate a number of bytes measured from a preceding control interval.

22 . The computer readable medium of claim 21 , wherein the code, when executed, is further to cause a computing device to transition to the other active link state.

23 . A system comprising:
a data link comprising a plurality of lanes; a first device; a second device coupled to the first device by the data link, wherein the second device is to:
send data to the first device within a first active link state, wherein at least a portion of the plurality of lanes are idle during the first active link state; and
send a data pattern to the first device to indicate a transition from the first active link state to a second active link state, wherein fewer lanes are to be idle in the second active link state than in the first active link state, the data pattern is to comprise start of data sequence (SDS) data to comprise a predefined sequence and a byte number value, and the byte number value is to indicate a number of bytes measured from a preceding control interval;
wherein the first device and second device are to transition to the second active link state based on the number of bytes.

24 . The system of claim 23 , wherein the data pattern is to further comprise an electrical ordered set and a series of training sequences, and the SDS is to end the data pattern.

25 . An apparatus comprising:
a power controller to send a request to another device to enter a low power state; a receiver to receive a negative acknowledgement to the request from the other device; and a timer to identify when a pre-determined retry period has ended, wherein the retry period is defined to restrict additional requests to the other device to enter the low power state within the retry period, and a start of the retry period is to correspond to transmission of the request.

26 . The apparatus of claim 25 , wherein the request is to be sent in a periodic control window embedded in a link layer data stream.

27 . The apparatus of claim 26 , wherein the retry period is to span at least two consecutive instances of the periodic control window.

28 . The apparatus of claim 27 , wherein the request is to be sent in a periodic control window, the negative acknowledgment is to be sent in a second periodic control window, and the retry period is to span a third and fourth periodic control window.

29 . The apparatus of claim 26 , wherein responses to requests to enter the low power state are to be sent in the periodic control window immediately subsequent to the periodic control window in which the corresponding request was sent.

30 . The apparatus of claim 25 , wherein the timer is to begin timing the pre-determined retry period from the requests to enter the idle state.

31 . The apparatus of claim 25 , wherein the receiver is further to send a

Assignees

• Intel Corp

Inventors

• Halleck William R
• Shah Rahul
• Iyer Venkatraman

Classifications

• G06F13/4282

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• G06F13/4027 Primary

  using bus bridges (G06F13/4022 takes precedence) · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• G06F13/1678

  using bus width · CPC title

• G06F13/124

  where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine · CPC title