Low pass filter embedded digital-to-analog converter

Patent metadata

Field	Value
Publication number	US-11115042-B1
Application number	US-202016952294-A
Country	US
Kind code	B1
Filing date	Nov 19, 2020
Priority date	Oct 9, 2020
Publication date	Sep 7, 2021
Grant date	Sep 7, 2021

Abstract

A low pass filter embedded digital-to-analog converter including a first switch coupled to a first node that is coupled to a fourth switch and a first capacitor, a second switch coupled to a second node that is coupled to the first capacitor and a third switch, a negative input of a first operational amplifier coupled to a third node that is coupled to the third switch and a second capacitor, and an output port of the first operational amplifier coupled to a fourth node that is coupled to the second capacitor and the fourth switch.

First claim

What is claimed is:

1. A circuit, comprising:
a first switch coupled to a first node that is coupled to a fourth switch and a first parallel array of binary-weighted linear capacitors;
a second switch coupled to a first voltage of common mode and a second node that is coupled to the first parallel array and a third switch;
a positive input port of a second operational amplifier coupled to a third node that is coupled to the third switch and a second capacitor;
a negative output port of the second operational amplifier coupled to a fourth node that is coupled to the second capacitor and the fourth switch;
a fifth switch coupled to a fifth node that is coupled to a second parallel array of binary-weighted linear capacitors and an eighth switch;
a sixth switch coupled to the first voltage of common mode and a sixth node that is coupled to the second parallel array and a seventh switch;
a negative input port of the second operational amplifier coupled to a seventh node that is coupled to the seventh switch and a fourth capacitor; and
a positive output port of the second operational amplifier coupled to an eighth node that is coupled to the fourth capacitor and the eighth switch;
wherein the first parallel array and the second capacitor are in series; wherein the second parallel array and the fourth capacitor are in series; and wherein the first parallel array and second parallel array are in parallel with each other.

2. The circuit in claim 1 , wherein a second voltage of common mode is coupled between the positive input port and the negative input port of the second operational amplifier.

3. The circuit in claim 1 , wherein the circuit is a 12-bit digital-to-analog converter.

4. The circuit in claim 1 , wherein the circuit is a fully differential analog signal outputting digital-to-analog converter.

5. A method, comprising:
receiving, by a digital-to-analog converter, a digital signal;
converting, by the digital-to-analog converter, the received digital signal to an analog signal;
filtering, by an embedded low pass filter in the digital-to-analog converter, the analog signal to remove a signal having a frequency higher than a predetermined threshold; and
outputting the filtered analog signal;
wherein the converter comprises:
a first switch coupled to a first node that is coupled to a fourth switch and a first parallel array of binary-weighted linear capacitors;
a second switch coupled to a first voltage of common mode and a second node that is coupled to the first parallel array and a third switch;
a positive input port of a second operational amplifier coupled to a third node that is coupled to the third switch and a second capacitor;
a negative output port of the second operational amplifier coupled to a fourth node that is coupled to the second capacitor and the fourth switch;
a fifth switch coupled to a fifth node that is coupled to a second parallel array of binary-weighted linear capacitors and an eighth switch;
a sixth switch coupled to the first voltage of common mode and a sixth node that is coupled to the second parallel array and a seventh switch;
a negative input port of the second operational amplifier coupled to a seventh node that is coupled to the seventh switch and a fourth capacitor; and
a positive output port of the second operational amplifier coupled to an eighth node that is coupled to the fourth capacitor and the eighth switch;
wherein the first parallel array and the second capacitor are in series; wherein the second parallel array and the fourth capacitor are in series; and wherein the first parallel array and second parallel array are in parallel with each other.

6. The method of claim 5 , wherein a second voltage of common mode is coupled between the positive input port and the negative input port of the second operational amplifier.

7. The method of claim 5 , wherein a first parallel array of binary-weighted linear capacitors is coupled between the first node and the second node, a second parallel array of binary-weighted linear capacitors is coupled between the fifth node and the sixth node.

8. The method of claim 5 , wherein the digital-to-analog converter is a 12-bit digital-to-analog converter.

9. The method of claim 5 , wherein the digital-to-analog converter outputs a fully differential analog signal.

Assignees

• Beken Corp

Inventors

• Hu Desheng
• Liu Jiazhou
• Guo Dawei

Classifications

• H03M1/804 Primary

  with charge redistribution · CPC title

• H03M1/76

  using switching tree · CPC title

• H03M1/68 Primary

  with conversions of different sensitivity, i.e. one conversion relating to the more significant digital bits and another conversion to the less significant bits · CPC title