Manufacturing method of TFT substrate and TFT substrate

Patent metadata

Field	Value
Publication number	US-11114567-B2
Application number	US-201916278718-A
Country	US
Kind code	B2
Filing date	Feb 19, 2019
Priority date	May 23, 2016
Publication date	Sep 7, 2021
Grant date	Sep 7, 2021

Abstract

A manufacturing method of TFT substrate and a TFT substrate are provided. The method provides a dual-gate structure symmetrically disposed on both sides of active layer, which prevents TFT threshold voltage from changing and improve TFT conduction state switching; by first manufacturing the active layer before the gate insulating layer to make the insulating layer directly grow on active layer, the contact interface between the gate insulating layer and active layer is improved, leading to further improving TFT conduction state switching. The TFT substrate makes the gate located between the source and the pixel electrode in vertical direction, and the dual-gate is symmetrically disposed on both sides of active layer to prevent TFT threshold voltage from changing and improve TFT conduction state switching, as well as improve the contact interface between the gate insulating layer and active layer, leading to further improving TFT conduction state switching.

First claim

What is claimed is:

1. A manufacturing method of thin film transistor (TFT) substrate, which comprises:
Step 1 : providing a base substrate, and forming a data line and a source connected to the data line on the base substrate;
Step 2 : forming an active layer, the active layer being at least partially above the source;
Step 3 : forming a gate insulating layer on top of the active layer, the source, the data line and the base substrate such that a portion of the gate insulating layer is directly formed on the top of the active layer to completely cover and directly contact entirety of the top of the active layer, and patternizing the gate insulating layer to form a first via corresponding to the active layer;
Step 4 : forming a first gate, a second gate and a drain, the first gate and the second gate being on the gate insulating layer and corresponding respectively to two lateral sides of the active layer, the drain being at least partially inside the first via and connected to the active layer through the first via;
Step 5 : forming a passivation layer on the drain, the first gate, the second gate and the gate insulating layer, patternizing the passivation layer to form a second via corresponding to the drain; and
Step 6 : forming a pixel electrode, the pixel electrode being at least partially inside the second via and connected to the drain through the second via,
wherein the drain is formed after the formation of the gate insulating layer and is filled in the first via of the gate insulating layer such that the connection between drain and the active layer is formed after the formation of the gate insulating layer; and
wherein the second via is located above and corresponding, in position, to the first via such that the second via is communication with the first via and a part of the pixel electrode that is located in the second via is in direct, electrical contact with a part of the drain that is located in the first via and an orthographic projection that is cast by the part of the pixel electrode located in the second via on the base substrate completely covers orthographic projections that are respectively cast by the part of drain located in the first via and the active layer on the base substrate.

2. The manufacturing method of TFT substrate as claimed in claim 1 , wherein Step 1 further comprises: depositing a first metal layer on the base substrate by physical vapor deposition, and using a lithography process to patternize the first metal layer to obtain the data line and the source connected to the data line; the lithography process comprising: photo-resist coating, exposure, development, and wet etching process;
Step 2 further comprises: depositing a semiconductor layer on the base substrate, data line and source by chemical or physical vapor deposition, and using a lithography process to patternize the semiconductor layer to obtain the active layer; the lithography process comprising: photo-resist coating, exposure, development, and wet etching process;
the data line and the source are made of one or more of the following: molybdenum, titanium, aluminum, copper; and
the active layer is made of amorphous silicon, polysilicon, or a metal oxide semiconductor.

3. The manufacturing method of TFT substrate as claimed in claim 1 , wherein Step 3 further comprises: depositing a first insulating layer on the active layer, source, data line and base substrate by chemical vapor deposition, and using a lithography process to patternize the first insulating layer to obtain the first via corresponding to the active layer to form the gate insulating layer; the lithography process comprising: photo-resist coating, exposure, development, and wet etching process;
the gate insulating layer is made of one or more of silicon oxide, and silicon nitride.

4. The manufacturing method of TFT substrate as claimed in claim 1 , wherein Step 4 further comprises: depositing a second metal layer on the gate insulating layer by physical vapor deposition, and using a lithography process to patternize the second metal layer to obtain the drain, the first gate and the second gate; the lithography process comprising: photo-resist coating, exposure, development, and wet etching process;
the drain, the first gate and the second gate are made of one or more of the following: molybdenum, titanium, aluminum, copper.

Assignees

• Shenzhen China Star Optoelect

Inventors

• Zhou Zhichao
• Xia Hui

Classifications

• H10P14/69433

  the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz · CPC title

• H10P14/69215

  the material being a silicon oxide, e.g. SiO2 · CPC title

• H10P95/00

  Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass · CPC title

• H10P76/2041

  Photolithographic processes · CPC title

• H10P50/692

  characterised by their composition, e.g. multilayer masks or materials · CPC title