Group III-V device structure

Patent metadata

Field	Value
Publication number	US-11114543-B2
Application number	US-201715460582-A
Country	US
Kind code	B2
Filing date	Mar 16, 2017
Priority date	Jan 24, 2017
Publication date	Sep 7, 2021
Grant date	Sep 7, 2021

Abstract

A group III-V device structure is provided. The group III-V device structure includes a channel layer formed over a substrate and an active layer formed over the channel layer. The group III-V device structure also includes a gate structure formed over the active layer and a source electrode and a drain electrode formed over the active layer. The source electrode and the drain electrode are formed on opposite sides of the gate structure. The group III-V device structure further includes a through via structure formed through the channel layer, the active layer and a portion of the substrate, and the through via structure is electrically connected to the source electrode or the drain electrode.

First claim

What is claimed is:

1. A group III-V device structure, comprising:
a channel layer formed over a substrate;
an active layer formed over the channel layer;
a doped structure formed over the active layer;
a first dielectric layer formed over the active layer and extends over the doped structure;
a gate electrode formed over the doped structure, wherein the gate electrode has an extending portion over the first dielectric layer, and the first dielectric layer is between the extending portion of the gate electrode and the doped structure;
a source electrode and a drain electrode formed over the active layer, wherein the source electrode and the drain electrode are formed on opposite sides of the gate electrode, and the doped structure is isolated from the source electrode by the first dielectric layer, wherein a bottom surface of the extending portion of the gate electrode is level with a top surface of the source electrode;
a through via structure formed through the channel layer, the active layer and a portion of the substrate, wherein the source electrode horizontally extends over and in direct contact with the through via structure, and the first dielectric layer is between the active layer and the source electrode, and the through via structure is through the first dielectric layer; and
a doped well region formed in a portion of the substrate and below the through via structure, wherein the doped well region surrounds a bottom portion of the through via structure.

2. The group III-V device structure as claimed in claim 1 , wherein the doped structure comprises:
a p-doped layer formed over the active layer; and
an n-doped layer formed over the p-doped layer.

3. The group III-V device structure as claimed in claim 1 , wherein the doped well region is doped with a first conductivity type, and the substrate is doped with a second conductivity type, and the first conductivity type is different from the second conductivity type.

4. The group III-V device structure as claimed in claim 1 , further comprising:
a transition layer over the substrate; and
a buffer layer over the transition layer, wherein the buffer layer is formed between the transition layer and the channel layer.

5. The group III-V device structure as claimed in claim 1 , further comprising:
a contact structure formed on the through via structure, wherein the bottom surface of the extending portion of the gate electrode is level with a top surface of contact structure.

6. The group III-V device structure as claimed in claim 1 , wherein the extending portion of the gate electrode is in direct contact with a topmost surface of the first dielectric layer.

7. The group III-V device structure as claimed in claim 1 , further comprising:
a second dielectric layer formed over the first dielectric layer, wherein a top surface of the second dielectric layer is leveled with a top surface of the gate electrode.

8. The group III-V device structure as claimed in claim 1 , wherein the first dielectric layer has a step height.

9. The group III-V device structure as claimed in claim 1 , further comprising:
a contact structure formed on the source electrode, wherein the contact structure is electrically connected to the through via structure by the source electrode.

10. The group III-V device structure as claimed in claim 9 , further comprising:
an interconnect structure formed on the contact structure, wherein the interconnect structure comprises a metal layer, and the metal layer of the interconnect structure is electrically connected to the through via structure by the contact structure.

11. A group III-V device structure, comprising:
a channel layer formed over a substrate;
an active layer formed over the channel layer;
a doped structure formed over the active layer;
a first dielectric layer formed over the active layer and covering an edge of the doped structure;
a gate electrode formed over the doped structure, wherein the first dielectric layer has a first portion, the first portion of the first dielectric layer covers the doped structure, and the gate electrode covers the first portion of the first dielectric layer;
a through via structure extending from the first dielectric layer to a portion of the substrate;
a conductive layer formed over the through via structure, wherein a top surface of the gate electrode is higher than a top surface of the conductive layer, wherein a top surface of the conductive layer is level with a top surface of the first portion of the first dielectric layer; and
a doped well region formed in a portion of the substrate and below the through via structure, wherein the doped well region surrounds a bottom portion of the through via structure, the doped well region is doped with a first conductivity type, the substrate is doped with a second conductivity type, and the first conductivity type is different from the second conductivity type.

12. The group III-V device structure as claimed in claim 11 , wherein the doped structure comprises:
a p-doped layer formed over the active layer; and
an n-doped layer formed over the p-doped layer.

13. The group III-V device structure as claimed in claim 11 , further comprising:
a transition layer over the substrate; and
a buffer layer over the transition layer, wherein the buffer layer is between the transition layer and the channel layer.

14. The group III-V device structure as claimed in claim 11 , further comprising:
a source electrode and a drain electrode formed over the active layer, wherein the source electrode and the drain electrode are on opposite sides of the gate electrode, and a top surface of the source electrode is leveled with the top surface of the conductive layer.

15. The group III-V device structure as claimed in claim 14 , further comprising:
a first contact structure formed on the source electrode, wherein the first contact structure is electrically connected to the through via structure by the conductive layer.

16. The group III-V device structure as claimed in claim 14 , further comprising:
an interconnect structure formed on the first contact structure, wherein the interconnect structure comprises a first metal layer and a top metal layer; and
a passivation layer formed over the interconnect structure, wherein the top metal layer is exposed by the passivation layer, and the first metal layer of the interconnect structure is electrically connected to the through via structure by the first contact structure.

17. A group III-V device structure, comprising:
a channel layer formed over a substrate;
an active layer formed over the channel layer;
a p-doped layer formed over the active layer;
a n-doped layer formed over the p-doped layer;
a first dielectric layer formed over the active layer;
a gate electrode formed over the n-doped layer, wherein the gate electrode is in direct contact with the n-doped layer;
a source electrode formed adjacent to the gate electrode, wherein the source electrode has an extending portion, and the extending portion of the source electrode covers a top surface of the first dielectric layer, and a top surface of the source electrode is level with a top surface of the first dielectric layer;
a through via structure formed in the substrate, wherein the extending portion of the source electrode extends over the through via structure, and
a doped well region formed in a portion of the substrate and below the through via structure, wherein the doped well region surrounds a bottom portion of the through via structure.

18. The group III-V devic

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chang Ming-Hong
• Chan Chih-Yuan
• Wang Shen-Ping
• Chen Chung-Cheng
• Kuo Chien-Li
• Chu Po-Tao

Classifications

• H10W74/137

  the encapsulations being directly on the semiconductor body (H10W74/134 takes precedence) · CPC title

• H10W20/425

  Barrier, adhesion or liner layers · CPC title

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title

• H10W20/023

  the interconnections being through-semiconductor vias · CPC title

• H10W20/021

  of interconnections within wafers or substrates · CPC title