Scalable-pixel-size image sensor

Patent metadata

Field	Value
Publication number	US-11114482-B2
Application number	US-202017100696-A
Country	US
Kind code	B2
Filing date	Nov 20, 2020
Priority date	Nov 20, 2019
Publication date	Sep 7, 2021
Grant date	Sep 7, 2021

Abstract

Photodetection elements within an integrated-circuit pixel array are dynamically configurable to any of at least three uniform-aspect-ratio, size-scaled pixel footprints through read-out-time control of in-pixel transfer gates associated with respective photodetection elements and binning transistors coupled between the transfer gates for respective clusters of the photodetection elements and a shared reset node.

First claim

What is claimed is:

1. An integrated-circuit pixel comprising:
four sets of photodetection elements, each of the sets disposed in a respective one of four sub-pixel quadrants defined by first and second orthogonal axes that traverse the integrated-circuit pixel;
four readout circuits each coupled to a respective one of the four sets of photodetection elements, each of the readout circuits having:
a floating diffusion node;
a first transfer gate coupled between the floating diffusion node and a constituent photodetection element of the respective one of the four sets of photodetection elements; and
an amplifier transistor having a gate terminal coupled to the floating diffusion node;

a shared reset node;
a reset transistor coupled between the shared reset node and a reset-voltage supply; and
a plurality of binning transistors each coupled between the shared reset node and the floating diffusion node of a respective one of the readout circuits.

2. The integrated-circuit pixel of claim 1 wherein each of the plurality of readout circuits comprises three additional transfer gates each coupled respectively between the floating diffusion node of the readout circuit and three further constituent photodetection elements within the respective one of the four sets of photodetection elements such that each of the readout circuits is coupled to a respective set of four of the photodetection elements, and wherein each set of four photodetection elements has a collective aspect ratio that nominally matches an aspect ratio of an individual photodetection element within the set of four photodetection elements.

3. The integrated-circuit pixel of claim 2 wherein the four sets of four photodetection elements have a collective aspect ratio that nominally matches the aspect ratio of each respective set of four of the photodetection elements.

4. The integrated-circuit pixel of claim 1 further comprising a capacitive element and a gain-control transistor coupled between the capacitive element and the shared reset node.

5. The integrated-circuit pixel of claim 4 wherein the gain-control transistor is coupled between the shared reset node and the reset transistor such that both the reset transistor and the gain-control transistor must be rendered to a drain-to-source conducting state to charge the shared-reset node via the reset-voltage supply.

6. An integrated-circuit image sensor comprising the integrated-circuit pixel of claim 4 and further comprising a control signal generator to:
assert first, second and third transfer-gate pulses at a gate terminal of the first transfer gate during successive first, second and third phases, respectively, of a multi-phase readout operation, each of the first, second and third transfer-gate pulses to enable photocharge transfer from the one of the photodetection elements to the floating diffusion node;
maintain the binning transistors and the gain-control transistor in a non-conducting state during the first phase of the multi-phase readout operation to implement a first conversion gain for the photocharge transfer enabled by the first transfer-gate pulse;
switch at least one of the binning transistors to a conducting state and maintaining the gain-control transistor in the non-conducting state during the second phase of the multi-phase readout operation to implement a second conversion gain for the photocharge transfer enabled by the second transfer-gate pulse, the second conversion gain being lower than the first conversion gain; and
switch the gain-control signal to the conducing state while the at least one of the binning transistors is in the conducting state during the third phase of the multi-phase readout operation to implement a third conversion gain for the photocharge transfer enabled by the third transfer-gate pulse, the third conversion gain being lower than the second conversion gain.

7. An integrated-circuit image sensor comprising the integrated-circuit pixel of claim 1 and further comprising a control signal generator to:
assert first and second transfer-gate pulses at a gate terminal of the first transfer gate during successive first and second phases, respectively, of a multi-phase readout operation, each of the first and second transfer-gate pulses to enable photocharge transfer from the one of the photodetection elements to the floating diffusion node;
maintain the binning transistors in a non-conducting state during the first phase of the multi-phase readout operation to implement a first conversion gain for the photocharge transfer enabled by the first transfer-gate pulse; and
switch at least one of the binning transistors to a conducting state during the second phase of the multi-phase readout operation to implement a second conversion gain for the photocharge transfer enabled by the second transfer-gate pulse, the second conversion gain being lower than the first conversion gain.

8. The integrated-circuit image sensor of claim 7 wherein the control signal generator additionally asserts, during each of first and second reset intervals that precede the first and second phases of the multi-phase readout operation, a control pulse on the reset transistor and a control pulse on at least one of the binning transistors to couple the reset-voltage supply to the floating diffusion node of at least one of the readout circuits.

9. The integrated-circuit image sensor of claim 7 wherein the control signal generator outputs control signals to reset constituent photodetection elements of each of the sets of photodetection elements at time-staggered offsets within an exposure interval.

10. An integrated-circuit image sensor comprising the integrated-circuit pixel of claim 1 and further comprising a color filter array having respective color filter elements disposed over the four sets of the photodetection elements and organized in a mosaic color pattern.

11. The integrated-circuit image sensor of claim 10 further comprising a micro-lens array having a respective micro-lens element disposed each constituent photodetection elements of each of the sets of photodetection elements.

12. The integrated-circuit pixel of claim 1 wherein each of the four readout circuits is coupled to a respective output line.

13. A method of operation within an integrated-circuit pixel having four sets of photodetection elements disposed in respective sub-pixel quadrants defined by first and second orthogonal axes that traverse the integrated-circuit pixel, a shared reset node, four floating diffusion nodes, four readout circuits coupled respectively to the four floating diffusion nodes, and four binning transistors coupled between the shared reset node and respective ones of the four floating diffusion nodes, the method comprising:
switching a reset transistor to a conducting state throughout a reset interval to couple the shared reset node to a reset-voltage supply; and
switching the binning transistors to conducting states during the reset interval to couple the respective floating diffusion nodes to the shared reset node such that each of the floating diffusion nodes is charged to a reset potential by the reset-voltage supply.

14. The method of claim 13 further comprising generating, via one of the readout circuits, a first output signal corresponding to the reset potential of the respective floating diffusion node.

15. The method of claim 14 wherein generating the first output signal comprises switching the binning transistors to a non-conducting state and generating the first output signal while the binning transistors remain in the non-conducting state.

16. The method of cl

Assignees

• Gigajot Tech Inc

Inventors

• Ma Jiaju
• Guidash Michael

Classifications

• H04N25/65

  applied to reset noise, e.g. KTC noise related to CMOS structures by techniques other than CDS · CPC title

• H04N25/59

  by controlling the amount of charge storable in the pixel, e.g. modification of the charge conversion ratio of the floating node capacitance · CPC title

• H04N25/778

  comprising amplifiers shared between a plurality of pixels, i.e. at least one part of the amplifier must be on the sensor array itself · CPC title

• H04N25/78

  Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters · CPC title

• H10F39/153

  Two-dimensional or three-dimensional array CCD image sensors · CPC title